Embedded Solutions
Page 9 of 37
Theory of Operation
The PMC-BiSerial-III RL1 features a Xilinx FPGA. The FPGA contains all of the
registers, FIFOs and protocol controlling elements of the PMC-BiSerial-III RL1 design.
Only the transceivers, switches and PLL circuit are external to the Xilinx device.
A logic block within the Xilinx controls the PCI interface to the host CPU. The PMC-
BiSerial-III RL1 design requires one wait state for read or writes cycles to any address.
The wait states refer to the number of clocks after the PCI core decodes the address
and control signals and before the “terminate with data” state is reached. Two
additional clock periods account for the delay to decode the signals from the PCI bus
and to convert the terminate-with-data state into the TRDY signal.
Scatter-gather DMA is provided for in this design with the memory page information
stored in host RAM as a series of chaining descriptors. Once the physical address of
the first chaining descriptor is written to the appropriate DMA pointer register, the
interface will read a 12-byte block from this location. The first four bytes comprise a
long-word indicating the physical address of the first block of the I/O buffer passed to
the read or write call. The next four bytes represent a long-word indicating the length of
that block. The final four bytes are a long-word indicating the physical address of the
next chaining descriptor along with two flag bits, in bit position 0 and 1. Bit zero is set to
a ‘1’ if this descriptor is the last in the chain. Bit one is set to a ‘1’ if the I/O transfer is
from the PMC-BiSerial-III RL1 board to host memory, and a ‘0’ if the transfer is from
memory to the board. These bits are then replaced with zeros to determine the address
of the next descriptor, if there is one.
To transmit data requires a number of steps to be performed. First, the PLL must be
programmed to supply the transmit clock. The data to be sent written to the TX FIFO
and the transmitter enabled. These steps do not need to be performed in this order, but
they must all be done to accomplish the transfer. If the requested transmit byte count is
zero, all the data written to the transmit FIFO will be sent, otherwise only the specified
number of bytes will be sent. The least significant byte of the FIFO word is sent first
then the next significant byte follows until the entire 32-bit word is sent. If a byte count
is requested that is not divisible by four, the remaining bytes of the last FIFO word are
discarded and a subsequent transmission will begin with the next FIFO word.
In order to receive data it is only necessary to configure the PLL, enable the receiver
and wait for data to be received. A 16-bit counter is incremented for each data byte
received. Once the reception has started, a 32-bit data word will be stored in the
receive FIFO for each four bytes received. The first byte is stored in the least significant
byte of the FIFO word and each subsequent byte is stored in the next most significant
byte. When the input data line is idle for at least eight bit-periods the reception will
terminate. This will cause the received byte count to be written to the byte count
register, clear the 16-bit byte counter and set the Receive Done status bit. If the last
FIFO word has not been completed, the last partial word will be written to the receive
