Embedded Solutions
Page 22 of 37
RL1_CHAN_0-7_RD_DMA_PNTR
[0x001C, 48, 74, A0, CC, F8, 124, 150] Read DMA Pointer (write only)
DMA Pointer Address Register
Data Bit
Description
31-0
First Chaining Descriptor Physical Address
FIGURE 10
PMC-BISERIAL-III RL1 READ DMA POINTER REGISTER
This write-only port is used to initiate a scatter-gather read DMA. When the address of
the first chaining descriptor is written to this port, the DMA engine reads three
successive long words beginning at that address. The first is the address of the first
memory block of the DMA buffer where the data from the device will be stored, the
second is the length in bytes of that block, and the third is the address of the next
chaining descriptor in the list of buffer memory blocks. This process is continued until
the end-of-chain bit in one of the next pointer values read indicates that it is the last
chaining descriptor in the list.
Note: Writing a zero to this port will abort a read DMA in progress.
RL1_CHAN_0-7_RX_FIFO_COUNT
[0x001C, 48, 74, A0, CC, F8, 124, 150] RX FIFO data count (read only)
RX FIFO Data Count Port
Data Bit
Description
31-12
Spare
11-0
RX Data Words Stored
FIGURE 11
PMC-BISERIAL-III RL1 RX FIFO DATA COUNT PORT
This read-only register port reports the number of 32-bit data words in the receive FIFO
and data pipeline (currently a maximum of 0x404).
