Embedded Solutions
Page 21 of 37
RL1_CHAN_0-7_WR_DMA_PNTR
[0x0018, 44, 70, 9C, C8, F4, 120, 14C] Write DMA Pointer (write only)
DMA Pointer Address Register
Data Bit
Description
31-0
First Chaining Descriptor Physical Address
FIGURE 8
PMC-BISERIAL-III RL1 WRITE DMA POINTER REGISTER
This write-only port is used to initiate a scatter-gather write DMA. When the address of
the first chaining descriptor is written to this port, the DMA engine reads three
successive long words beginning at that address. The first is the address of the first
memory block of the DMA buffer containing the data to write to the device, the second is
the length in bytes of that block, and the third is the address of the next chaining
descriptor in the list of buffer memory blocks. This process is continued until the end-of-
chain bit in one of the next pointer values read indicates that it is the last chaining
descriptor in the list.
Note: Writing a zero to this port will abort a write DMA in progress.
RL1_CHAN_0-7_TX_FIFO_COUNT
[0x0018, 44, 70, 9C, C8, F4, 120, 14C] TX FIFO data count (read only)
TX FIFO Data Count Port
Data Bit
Description
31-12
Spare
11-0
TX Data Words Stored
FIGURE 9
PMC-BISERIAL-III RL1 TX FIFO DATA COUNT PORT
This read-only register port reports the number of 32-bit data words in the transmit FIFO
and data holding register (currently a maximum of 0x401).