Dynamic Engineering PMC-BISERIAL-III RL1, Руководство пользователя

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Address Map
Register Name Offset Description
RL1_BASE_CONTROL 0x0000 Base Control Register
RL1_PLL_WRITE 0x0000 Base Control - Bits 16-19 Used for PLL Control
RL1_PLL_READ 0x0004 Switch Port Bit 19 Used for pll_sdat Input
RL1_USER_SWITCH 0x0004 User Switch Read Port and Xilinx Design Revision
RL1_CHAN_0_CONTROL 0x0010 Channel 0 Control Register
RL1_CHAN_0_STATUS 0x0014 Channel 0 Status Register
RL1_CHAN_0_WR_DMA_PNTR 0x0018 Channel 0 Write DMA Physical PCI dpr Address
RL1_CHAN_0_TX_FIFO_COUNT 0x0018 Channel 0 TX FIFO Count
RL1_CHAN_0_RD_DMA_PNTR 0x001C Channel 0 Read DMA Physical PCI dpr Address
RL1_CHAN_0_RX_FIFO_COUNT 0x001C Channel 0 RX FIFO Count
RL1_CHAN_0_FIFO 0x0020 Channel 0 FIFO Single-Word Access
RL1_CHAN_0_TX_AMT_LVL 0x0024 Channel 0 TX almost empty level
RL1_CHAN_0_RX_AFL_LVL 0x0028 Channel 0 RX Almost Full Level
RL1_CHAN_0_TX_CONTROL 0x002C Channel 0 TX Control Register
RL1_CHAN_0_RX_CONTROL 0x0030 Channel 0 RX Control Register
RL1_CHAN_0_TX_START 0x0034 Channel 0 TX Start Latch
RL1_CHAN_0_RX_START 0x0038 Channel 0 RX Start Latch
RL1_CHAN_0_RX_BYTE_COUNT 0x0038 Channel 0 RX Byte Count
RL1_CHAN_1_CONTROL 0x003C Channel 1 Control Register
RL1_CHAN_1_STATUS 0x0040 Channel 1 Status Register
RL1_CHAN_1_WR_DMA_PNTR 0x0044 Channel 1 Write DMA Physical PCI dpr Address
RL1_CHAN_1_TX_FIFO_COUNT 0x0044 Channel 1 TX FIFO Count
RL1_CHAN_1_RD_DMA_PNTR 0x0048 Channel 1 Read DMA Physical PCI dpr Address
RL1_CHAN_1_RX_FIFO_COUNT 0x0048 Channel 1 RX FIFO Count
RL1_CHAN_1_FIFO 0x004C Channel 1 FIFO Single-Word Access
RL1_CHAN_1_TX_AMT_LVL 0x0050 Channel 1 TX almost empty level
RL1_CHAN_1_RX_AFL_LVL 0x0054 Channel 1 RX Almost Full Level
RL1_CHAN_1_TX_CONTROL 0x0058 Channel 1 TX Control Register
RL1_CHAN_1_RX_CONTROL 0x005C Channel 1 RX Control Register
RL1_CHAN_1_TX_START 0x0060 Channel 1 TX Start Latch
RL1_CHAN_1_RX_START 0x0064 Channel 1 RX Start Latch
RL1_CHAN_1_RX_BYTE_COUNT 0x0064 Channel 1 RX Byte Count
RL1_CHAN_2_CONTROL 0x0068 Channel 2 Control Register
RL1_CHAN_2_STATUS 0x006C Channel 2 Status Register
RL1_CHAN_2_WR_DMA_PNTR 0x0070 Channel 2 Write DMA Physical PCI dpr Address
RL1_CHAN_2_TX_FIFO_COUNT 0x0070 Channel 2 TX FIFO Count
RL1_CHAN_2_RD_DMA_PNTR 0x0074 Channel 2 Read DMA Physical PCI dpr Address
RL1_CHAN_2_RX_FIFO_COUNT 0x0074 Channel 2 RX FIFO Count
RL1_CHAN_2_FIFO 0x0078 Channel 2 FIFO Single-Word Access
RL1_CHAN_2_TX_AMT_LVL 0x007C Channel 2 TX almost empty level
RL1_CHAN_2_RX_AFL_LVL 0x0080 Channel 2 RX Almost Full Level
RL1_CHAN_2_TX_CONTROL 0x0084 Channel 2 TX Control Register
RL1_CHAN_2_RX_CONTROL 0x0088 Channel 2 RX Control Register
RL1_CHAN_2_TX_START 0x008C Channel 2 TX Start Latch
RL1_CHAN_2_RX_START 0x0090 Channel 2 RX Start Latch
RL1_CHAN_2_RX_BYTE_COUNT 0x0090 Channel 2 RX Byte Count
RL1_CHAN_3_CONTROL 0x0094 Channel 3 Control Register
RL1_CHAN_3_STATUS 0x0098 Channel 3 Status Register
RL1_CHAN_3_WR_DMA_PNTR 0x009C Channel 3 Write DMA Physical PCI dpr Address
RL1_CHAN_3_TX_FIFO_COUNT 0x009C Channel 3 TX FIFO Count
RL1_CHAN_3_RD_DMA_PNTR 0x00A0 Channel 3 Read DMA Physical PCI dpr Address
RL1_CHAN_3_RX_FIFO_COUNT 0x00A0 Channel 3 RX FIFO Count
RL1_CHAN_3_FIFO 0x00A4 Channel 3 FIFO Single-Word Access
RL1_CHAN_3_TX_AMT_LVL 0x00A8 Channel 3 TX almost empty level
RL1_CHAN_3_RX_AFL_LVL 0x00AC Channel 3 RX Almost Full Level
RL1_CHAN_3_TX_CONTROL 0x00B0 Channel 3 TX Control Register
RL1_CHAN_3_RX_CONTROL 0x00B4 Channel 3 RX Control Register
RL1_CHAN_3_TX_START 0x00B8 Channel 3 TX Start Latch
RL1_CHAN_3_RX_START 0x00BC Channel 3 RX Start Latch
RL1_CHAN_3_RX_BYTE_COUNT 0x00BC Channel 3 RX Byte Count
RL1_CHAN_4_CONTROL 0x00C0 Channel 4 Control Register