Embedded Solutions
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BA22_CHAN_READY_CNT
[0x24] Tx Ready Count(read/write)
Tx Ready Count Register
Data Bit
Description
31-0
Amount of data required to start transmission
Figure 19 PcieBiSerialDb37BA22 TX Ready Count Register
This read/write port accesses the Ready Count register. When the number of data
words in the transmit data FIFO is greater or equal to this value, the FIFO READY
signal to the TX State Machine will be set.
BA22_CHAN_FRAME_REF
[0x28] Tx Frame Ref(read/write)
Tx Frame Period Register
Data Bit
Description
31-0
Set Frame Period
Figure 20 PcieBiSerialDb37BA22 TX Frame Reference Register
This read/write port accesses the Frame Reference register. PLLA clock is the time
base. 73.636 MHz for BA22. This corresponds to 13.58 nS per period. The Frame
repetition rate is the number set in the reference * the period. Please note: There is a
SW hazard if the frame period is set shorter than the transmission time of the
programmed frame. The State Machine will send the programmed frame and then wait
for the next Frame Start pulse [comes at the start of each programmed frame time]. If
the value is programmed too small / too much data the HW will miss the frame start and
wait for the next one.
Also the period is in terms of the clock rather than pixels so it is possible to create
frames that are on pixel time or something non-integer.