Embedded Solutions
Page 9
start sending the second, third
…
. frames. Once started if the data FIFO is empty when
the transmitter is ready to read the next data set, an error for underflow is flagged. The
error can cause an interrupt if desired.
An additional feature is programmable IDLE pattern output. When IDLEs are enabled in
the control register the transmitter will begin transmitting IDLEs whenever the state-
machine is enabled. When IDLEs are not enabled, IDLEs are still transmitted between
lines and frames, but not when the transmitter is not active.
The receiver uses the received clock to capture data with a small state-machine that
loads the data into 2 parallel shift registers. Data from the shift registers is combined to
form pixels. In addition the upper bit [D15] is set when a frame boundary is
encountered. D14 is set for each line received. Frame detection is based on either the
Sync or PreAmble patterns being detected – next data pixel is then marked. Lines are
marked when Idles are detected, again on the next data pixel. If the IDLE pattern is the
same as the SYNC pattern all lines will be marked as having both Frame and Line.
Two pixels are stored to make a 32 bit quantity before moving to the first storage FIFO.
The reference rate of the input to the FIFO is the receive clock.
The read side of the first receive FIFO is tied to the input side of a 1Kx32 FIFO. The
second FIFO is used to support the receive DMA action.
The second FIFO has two sources. The transmit data chain can be looped back from a
point between the second discrete FIFO and the final transmission FIFO to the DMA
FIFO. With the Bypass bit set data loaded into the TX side can be read from the RX
side for an internal BIT. The first receive and last transmit stages are the only missing
pieces.
Both the transmitter and receiver allow for pixel reversal. The data is stored as 32 bit
words into the transmit FIFO from the system or the receive FIFO from the interface.
The pixel stored into the D15-0 or D31-16 can be transmitted first depending on the
selection of the transmit data order. Similarly the receive side data order can be
reversed if needed.
Custom cables can be manufactured to your requirements. The loop-back IO
definitions are toward the end of this manual. Please contact Dynamic Engineering with
your specifications.
In the “BA22” design the Termination and Direction controls are set in the VHDL for the
IO. The received signals are terminated and the transmitted signals are not.
All of the IO is routed through the FPGA to allow for custom applications. Larger
external and internal FIFO’s and Dual Ported memories are implemented for this
