Embedded Solutions
Page 25
BA22_CHAN_STATUS
[0x4] Channel Status Read/Clear Latch Write Port
Channel Status Register
Data Bit
Description
31
Interrupt Status
30
LocalInt
29
Transmitter Idle
28-27
spare
26
Tx DMA FIFO AFL
25
Tx DMA FIFO AMT
24
spare
23
BurstInIdle
22
BurstOutIdle
21
Ext FIFO 1 FULL
20
Ext FIFO 0 FULL
19
spare
18
RxFifoOvFlLat
17
TxFifoUnFlLat
16
TX FRAME DONE LAT
15
Read DMA Interrupt Occurred
14
Write DMA Interrupt Occurred
13
Read DMA Error Occurred
12
Write DMA Error Occurred
11
RxAFLvlIntLat
10
TxAELvlIntLat
9
EXT FIFO 1 MT
8
EXT FIFO 0 MT
7
spare
6
Rx FIFO Full
5
Rx FIFO Almost Full – complete chain
4
Rx FIFO Empty
3
Spare
2
Tx FIFO Full
1
Tx FIFO Almost Empty – complete chain
0
Tx FIFO Empty
Figure 11 PcieBiSerialDb37BA22 Channel STATUS PORT
BA22 FIFO: A 4K x 32 FIFO’s and a 1Kx32 FIFO are used to create the internal Rx
memory. The Tx side uses a combination of internal block RAM FIFO and two discrete
128Kx32 FIFO’s. The status for the Tx FIFO and Rx FIFO refer to these FIFO’s. The
