Embedded Solutions
Page 29
BA22_CHAN_WR_DMA_PNTR
[0x8] Write DMA Pointer (write only)
BurstIn DMA Pointer Address Register
Data Bit
Description
31-2
First Chaining Descriptor Physical Address
1
direction [0]
0
end of chain
Figure 12 PcieBiSerialDb37BA22 Write DMA pointer register
This write-only port is used to initiate a scatter-gather write [TX] DMA. When the
address of the first chaining descriptor is written to this port, the DMA engine reads
three successive long words beginning at that address. Essentially this data acts like a
chaining descriptor value pointing to the next value in the chain.
The first is the address of the first memory block of the DMA buffer containing the data
to read into the device, the second is the length in bytes of that block, and the third is
the address of the next chaining descriptor in the list of buffer memory blocks. This
process is continued until the end-of-chain bit in one of the next pointer values read
indicates that it is the last chaining descriptor in the list.
All three values are on LW boundaries and are LW in size. Addresses for successive
parameters are incremented. The addresses are physical addresses the HW will use
on the PCI bus to access the Host memory for the next descriptor or to read the data to
be transmitted. In most OS you will need to convert from virtual to physical. The length
parameter is a number of bytes, and must be on a LW divisible number of bytes.
Status for the DMA activity can be found in the channel control register and channel
status register.
Notes:
1. Writing a zero to this port will abort a write DMA in progress.
2. End of chain should not be set for the address written to the DMA Pointer
Address Register. End of chain should be set when the descriptor follows the
last length parameter.
3. The Direction should be set to ‘0’ for Burst In DMA in all chaining descriptor
locations.
