Embedded Solutions
Page 21
BA22_BASE_PLL_WRITE
BA22_BASE_PLL_READ
[$10 Board level PLL FIFO Port]
DATA BIT
DESCRIPTION
31-0
LW written to / read from PLL
Figure 9 PcieBiSerialDb37BA22 PLL FIFO Port Bit Map
The transmit FIFO is monitored by the PLL state-machine. When the FIFO is written to
the first word is read by the state-machine and parsed. The first word contains the
mode on bit 0, address on 7-1, length on 15-8 [1-255], and the first byte or two to
transfer. If multiple bytes – 3 or more are to be transferred the SW will need to make
sure the data is in the FIFO for the 2
nd
LW before the end of the processing of the 2
nd
byte or an underflow condition will be detected. If your system timing is tough to
manage it is suggested to disable the SM, load the FIFO and then enable the SM. A
status bit for the idle condition is available to allow SW to know when the SM has
responded to the disable.
The Length is the number of bytes in the data portion of the m 1.
Please note: The PLL’s have two data sets written to two address offsets per PLL
programmed. The UserAp automatically converts the .jed file from the Cypress tool
and generates the local buffers with the hex data to load to the PLL. The application
software loads the FIFO with the correct address, length and data x2 for a complete
programming operation.
The State-machine will parse the message and write or read based on bit 0. In either
case the address and R/W are transmitted. An ACK is looked for from the Target. If a
Write the data is then transmitted with the ACK being checked after each byte.
Clocking is continuous until the message is completed. If a read is implemented, clocks
are generated without data after the address. Data is captured during the high portion
of the clock cycle, and the Master asserts the ACK until the last byte where a NAK is
asserted. Data is stored into the receive FIFO in this case.
The reference software has examples of working with the PLL’s and controlling HW.
