Dynamic Engineering PCIeBiSerialDb37-BA22, Руководство пользователя

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Embedded Solutions Page 14
Address Map
Base Address Map
Function Offset
// PCIeBiSerialDb37BA22 BASE definitions
#define BA22_BASE_BASE 0x0000 // 0 BA22Base Base control register
#define BA22_BASE_USER_SWITCH 0x0004 // 1 BA22Base User DIP switch read
#define BA22_BASE_XILINX_REV 0x0004 // 1 BA22Base Xilinx revision read port
#define BA22_BASE_XILINX_DES 0x0004 // 1 BA22Base Xilinx design read port
#define BA22_BASE_STATUS 0x0008 // 2 BA22Base status Register offset
#define BA22_BASE_PLL_WRITE 0x0000 // 4 BA22Base PLL FIFO write port
#define BA22_BASE_PLL_READ 0x0000 // 4 BA22Base PLL FIFO read port
Figure 4 PCIeBiSerialDb37BA22 Internal Address Map Base Functions
The address map provided is for the local decoding performed within
PcieBiserialDb37BA22. The addresses are all offsets from a base address. Dynamic
Engineering prefers a long-word oriented approach because it is more consistent across
platforms.
The map is presented with the #define style to allow cutting and pasting into many
compilers “include” files.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0xDCBA and the CardId = 0x0052 for the
PcieBiSerialDb37BA22.
The BA22 design has 1 channel implemented at this time. The BASE contains the
common elements of the design, while the Channels have the IO specific interfaces.
The BASE starts at the card offset. Channel 0 starts at register 20
Section
Register Address Range COM name
(starting Hex address)
Base 0-19 (0x0000) PLL, Switch, Status
Channel 0 20-39 (0x0050) BA22 Transmitter & Receiver