Embedded Solutions
Page 18
Base Register Definitions
BA22_BASE_BASE
[$00 Base Control Register Port read/write]
DATA BIT
DESCRIPTION
31-2
spare
1
ClrPll
0
PllProgEn
Figure 6 PcieBiSerialDb37BA22 Control Base Register Bit Map
This is the base control register for the BA22. The features common to all channels are
controlled from this port. Unused bits are reserved for additional new features. Unused
bits should be programmed ‘0’ to allow for future commonality.
PllProgEn: When this bit is set to a one, the state-machine used to program the PLL is
enabled to operate.
ClrPll: when set the PLL and associated memories are cleared. Must be returned to
cleared for normal operation.
The PLL is programmed with the output file generated by the Cypress PLL
programming tool. [CY3672 R3.01 Programming Kit or CyberClocks R3.20.00 Cypress
may update the revision from time to time.] The .JED file is used by the Dynamic Driver
to program the PLL. Programming the PLL is fairly involved and beyond the scope of
this manual. For clients writing their own drivers it is suggested to get the Engineering
Kit for this board including software, and to use the translation and programming files
ported to your environment. This procedure will save you a lot of time. For those who
want to do it themselves the Cypress PLL in use is the 22393. The output file from the
Cypress tool can be passed directly to the Dynamic Driver [Linux or Windows] and used
to program the PLL without user intervention.
The reference frequency for the PLL is 25 MHz.