Cypress EX-USB FX3, Руководство программиста

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46 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Overview
Figure 3-19. DMA Adaptor
3.11 Power
3.11.1 Power Domains
Power supply domains in FX3 can be mainly classified in four - Core power domain, Memory power
domain, IO power domain, and Always On power domain
Core power domain encompasses a large section of the device including the CPU, peripheral logic,
and the interconnect fabric. The system SRAM memory resides in the Memory power domain. IO
logic dwell in their respective peripheral IO power domain (either of the I
2
C IO power domain,
I2S-UART IO -SPI IO-GPIO power domain, Clock IO power domain, USB IO power domain, and
Processor Port IO power domain). The Always On power domain hosts the power management
controller, different wake-up sources and their associated logic.
Wake-up sources forces a system in suspend or standby state to switch to the normal power
operation mode. These are distributed across peripherals and configured in the 'Always On global
configuration block'. Some of them include level match on level sensitive wakeup IOs, toggle on
edge sensitive wake-up IOs, activity on the USB 2.0 data lines, OTG ID change, LFPS detection on
USB 3.0 RX lines, USB connect event, and watchdog timer - timeout event.
The 'Always On global configuration block' runs off the standby clock and will be turned off only in
the lowest power state (core power down).
3.11.2 Power Management
At any instant, FX3 is in one of the four power modes - normal, suspend, standby, or core power
down. In a typical scenario, when FX3 is actively executing its tasks, the system is in normal mode.
The usual clock gating techniques in peripherals minimize the overall power consumption.
On detecting prolonged periods of inactivity, the chip can be forced to enter the suspend mode. All
ongoing port (peripheral) activities are wrapped up, ports disabled, and wake up sources are set
before entering the suspend state. In applications involving USB 3.0, the USB3 PHY is forced into
the U3 state. USB2PHY, if used, is forced into suspend. The System RAM transitions to a low power
stand by state; read and write to RAM cannot be performed. The CPU is forced into the halt state.
The ARM core will retain its state, including the Program Counter inside the CPU. All clocks except
the 32-KHz standby are turned off by disabling the System PLL is through the global configuration
block. In the absence of clocks, the IO pins can be frozen to retain their state as long as the IO
power domain is not turned off The INT# pin can be configured to indicate FX3's presence in low
power mode.
Further reduction in power is achieved by forcing FX3 into stand-by state where, in addition to
disabling clocks, the core power domain is turned off. As in the case of suspend, IO states of
powered peripheral IO domains are frozen and ports disabled. Essential configuration registers of
Core Logic
Block XYZ
I / O
Pads
DMA / Bus
Adapter
Wake Up
Logic
I / O
Matrix
Sy
st
em
In
te
rc
onnec
ts
Block XYZ
Clock Domain
Always - On
Clock / Power / Reset Domain
Processor / Bus
Clock Domain
wakeup
Block XYZ Power Domain
Core Logic
Block XYZ
I / O
Pads
DMA / Bus
Adapter
Wake Up
Logic
I / O
Matrix
Sy
st
em
In
te
rc
onnec
ts
Block
XYZ
Clock
Domain
Always - On
Clock / Power / Reset Domain
Processor / Bus
Clock Domain
wakeup
Block XYZ Power Domain
(a) Core Clock >Bus clock (b) Bus clock>Core Clock