Cypress EX-USB FX3, Руководство программиста

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122 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.4.3 SPI_INTR register
This register reflects the status of SPI related interrupt sources.
9.1.4.4 SPI_INTR_MASK register
This register is used to enable/disable the reporting of SPI interrupts to the ARM CPU.
6 ERROR RW1S RW1C 0
An internal error has occurred with cause
ERROR_CODE.
Sticky. Must be cleared by software.
27:24 ERROR_CODE W R 0xF
Error code. Only relevant when ERROR=1.
ERROR logs only the FIRST error to occur
and will never change value as long as
ERROR=1.
12: TX FIFO overflow
13: RX FIFO underflow
15: No error
28 BUSY W R 0
Indicates the block is busy transmitting data.
This field may remain asserted after the block
is suspended and must be polled before
changing any configuration values.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE RW1S RW1C 0
Set when SPI_STATUS.RX_DONE asserts,
cleared by software.
1 RX_DATA RW1S RW1C 0
Set when SPI_STATUS.RX_DATA asserts,
cleared by software.
2 RX_HALF RW1S RW1C 0
Set when SPI_STATUS.RX_HALF asserts,
cleared by software.
3 TX_DONE RW1S RW1C 0
Set when SPI_STATUS.TX_DONE asserts,
cleared by software.
4 TX_SPACE RW1S RW1C 0
Set when SPI_STATUS.TX_SPACE asserts,
cleared by software.
5 TX_HALF RW1S RW1C 0
Set when SPI_STATUS.TX_HALF asserts,
cleared by software.
6 ERROR RW1S RW1C 0
Set when SPI_STATUS.ERROR asserts,
cleared by software.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE R RW 0
1: Enable the reporting of
SPI_INTR.RX_DONE interrupt to CPU
1 RX_DATA R RW 0
1: Enable the reporting of
SPI_INTR.RX_DATA interrupt to CPU
2 RX_HALF R RW 0
1: Enable the reporting of
SPI_INTR.RX_HALF interrupt to CPU
3 TX_DONE R RW 0
1: Enable the reporting of
SPI_INTR.TX_DONE interrupt to CPU
4 TX_SPACE R RW 0
1: Enable the reporting of
SPI_INTR.TX_SPACE interrupt to CPU
Bits Field Name
HW
Access
SW
Access
Default
Value
Description