Cypress EX-USB FX3, Руководство программиста

Страница: 127 / 192

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 127
FX3 Serial Peripheral Register Access
9.2.4 Gpio_invalue1 Register
Input state of the GPIO 32-60. Each bit indicates the state of GPIO. The upper three bits are
reserved.
9.2.5 GPIO_INTR0 Register
This register holds the interrupt state of each GPIO 0 -31. These bits are valid only for those GPIOs
configured as simple GPIO.3.
9.2.6 GPIO_INTR1 Register
This register holds the interrupt state of each GPIO 32 -60. The upper three bits are reserved. These
bits are valid only for those GPIOs configured as simple GPIO.
9.3 Complex GPIO (PIN) Registers
The following table lists key registers of the complex GPIO interface.
Table 9-2. Complex GPIO Registers
The following table lists the pins registers for complex GPIO interface.
Bits Name HW SW Default Description
28:0 INVALUE1 W R 0 If bit <x> is set, state of GPIO <x + 32>is high.
Bits Name HW SW Default Description
31:0 INTR0 W R 0 If bit <x> is set, interrupt for GPIO <x> is active.
Bits Name HW SW Default Description
28:0 INTR1 W R 0 If bit <x> is set, interrupt for GPIO <x + 32>is active.
Address Qty Width Name Description
0xE0
(GPIO_ID MOD
8) * 0x10
8 128 PIN
General purpose I/O registers (one pin)
a
a. See table 3 for further break up of each 128 bit register.
0xE00013E8 1 32 GPIO_PIN_INTR GPIO interrupt vector for PINs