Cypress EX-USB FX3, Руководство программиста

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144 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 P-Port Register Access
Figure 10-7. Long Transfer With Integral Number Of Buffers
The following should be noted:
The transfer is setup in the P-port socket by the Benicia CPU, resulting in SOCK_STAT[N] asserting
at some point into the transfer to initiate transfer of the first buffer.
The AP initiates the transfer by writing DMA_ENABLE=1, LONG_TRANSFER=1 along with
DMA_SOCK and DMA_DIRECTION to DMA_XFER. This may take place before, during or after
SOCK_STAT[N] asserts.
When both SOCK_STAT[N] and DMA_ENABLE are asserted, DMA_READY and DMA_WMARK
assert.
The AP now transfers data in full bursts until DMA_WMARK de-asserts. Each time this happens, the
AP must wait until DMA_READY and DMA_WMARK re-assert.
When enough data is transferred, the AP must terminate the transfer by writing DMA_ENABLE=0.
10.4.6 Long Transfer – Aborted by AP
A long transfer can be aborted by AP by writing DMA_ENABLE=0 at any time and follow it with a
mailbox message to wrap up the partially written buffer.
The following diagram illustrates the working of an aborted long transfer:
Figure 10-8. Aborted Long Transfer
The following should be noted:
DMA_WMARK de-asserts when either DMA_ENABLE is cleared or the configured water mark posi-
tion is reached, whichever occurs sooner.
DMA_
XFER
DMA_READY
SOCK_STAT[N]
A/D
R/W#
DMA_
XFER
DMA_ENABLE
DMA_WMARK
Buffer N
Burst 1
Buffer N
Burst 0
Buffer N
Burst 3
Buffer N
Burst 2
Buffer 0
Burst 1
Buffer 0
Burst 0
Buffer 0
Burst 3
Buffer 0
Burst 2
DMA_READY
SOCK_STAT[N]
A/D
R/W#
DMA_
XFER
DMA_ENABLE
DMA_WMARK
N
2 DMA_
XFER
Buffer 0
Burst 1
Buffer 0
Burst 0
Buffer 0
Burst 3
Buffer 0
Burst 2
Buffer N
Burst 1
Buffer N
Burst 0