Cypress EX-USB FX3, Руководство программиста

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24 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Overview
the core to facilitate low latency access to frequently used areas of code and data memory. In
addition, the two tightly coupled memories (TCM) (one each for data and instruction) associated with
the core provide a guaranteed low latency memory (without cache hit or miss uncertainties).
The ARM926 CPU contains a full Memory Management Unit (MMU) with virtual to physical address
translation. FX3 contains 8 KB of data and instruction caches. ARM926-EJS has 4-way set
associative caches and cache lines are 32 bytes wide. Each set therefore has 64 cache lines.
Interrupts vectored into one of the FIQ or IRQ request lines provide a method to generate interrupt
exceptions to the core.
A built-in logic provides an integrated on-chip JTAG based debug support for the processor core.
Figure 3-1. Key CPU Features
3.2 Interconnect Fabric
The Advanced Microcontroller Bus Architecture - Advanced High Performance Bus (AMBA AHB)
interconnect forms the central nervous system of FX3. This fabric allows easy integration of
processors, on-chip memories, and other peripherals using low power macro cell functions while
providing a high-bandwidth communication link between elements that are involved in majority of the
transfers. This multi-master high bandwidth interconnect has the following components:
■
AHB bus master(s) that can initiate read and write operations by providing an address and
control information. At any given instant, a bus can at most have one owner. When multiple
masters demand bus ownership, the AHB arbiter block decides the winner.
■
AHB bus slave(s) that respond to read or write operations within a given address-space range.
The bus slave signals back to the active master the success, failure, or waiting of the data
transfer. An AHB decoder is used to decode the address of each transfer and provide a select
signal for the slave that is involved in the transfer.
■
AHB bridges in the system to translate traffic of different frequency, bus width, and burst size.
These blocks are essential in linking the buses
■
AHB Slave/Master interfaces: These macro cells connect peripherals, memories, and other
elements to the bus.
ARM926EJS
Instr
TCM
(16 KB)
Data
TCM
(8 KB)
Instr
Cache
(8 KB)
Data
Cache
(8 KB)
nFIQ
nIRQ
Arm TCM
200 MHz x32-bit
1 cy accesses
Arm TCM
200 MHz x32-bit
1 cy accesses
2 x AHB
200 MHz x 32b
1,8 cy bursts
1,4,8 cy bursts
JTAG
Debug
Logic
JTAG
Signals