Cypress EX-USB FX3, Руководство программиста

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FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 139
FX3 P-Port Register Access
10.4 Transferring Data into and out of Sockets
The following section describes how the Application Processor transfers blocks of data into and out
of active sockets using the PP Register protocol. All GPIF PP-Mode based transfers use the same
internal mechanisms but may differ in the usage of DRQ/INTR signaling.
We will look here at how read and write transfers are implemented for full buffer, partial buffer, zero-
length packets and long transfers. We will make a distinction between short (single buffer) and long
(multiple buffer) transfers. For long transfer it is assumed that a higher level protocol (e.g. through
use of mailboxes) has communicated the need for transfer of large size between AP and ARM CPU.
All transfers are based on the following command, config and status bits on PP_* interface:
1.
PP_SOCK_STAT.SOCK_STAT[N]
. For each socket this status bit indicates that a socket has a
buffer available to exchange data (it has either data or space available).
2.
PP_DMA_XFER.DMA_READY
. This status bit indicates whether the P-Port is ready to service
reads from or writes to the active socket (the active socket is selected through the
PP_DMA_XFER register). PP_EVENT.DMA_READY_EV mirrors
PP_DMA_XFER.DMA_READY with a short delay of a few cycles.
3.
PP_EVENT.DMA_WMARK_EV.
This status bit is similar to DMA_READY, but it de-asserts a pro-
grammable number of words before the current buffer is completely exchanged. It can be used to
create flow control signals with offset latencies in the signaling interface.
4.
PP_DMA_XFER.LONG_TRANSFER.
This config bit indicates if long (multi-buffer) transfers are
enabled. This bit is set by Application Processor as part of transfer initiation.
5.
PP_DMA_XFER.DMA_ENABLE.
This command and status indicates that DMA transfers are
enabled. This bit is set by Application Processor as part of transfer initiation and cleared by Beni-
cia hardware upon transfer completion for short transfers and by Application Processor for long
transfers.
10.4.1 Bursting and DMA_WMARK
AP transfers data on the interface in bursts of 1 or more words at a time. The burst size for transfers
may be configured to be any power of 2 words.
The DMA_WMARK status is generated in the GPIF controller counting back a configurable number
of words from the end of the last burst needed to transfer all the data for a buffer (this may be fewer
bursts than fit the maximum buffer size).
Burst size and watermark distance is programmable across a range of values.
10.4.2 Short Transfer - Full Buffer
A full size write (ingress) transfer is defined as a transfer that fills the entire buffer space available. If
this buffer space is known in advance (due to higher level protocol), it is not required to read
DMA_SIZE.
A full size read (egress) transfer is defined as a transfer that reads all the available data from the buf-
fer – this may be less than the actual max buffer size.
Note
In the figures that illustrate transfers:
Values of SOCK_STAT[N], DMA_ENABLE, DMA_READY and DMA_WMARK are shown as signals;
these are really values of status bits in PP_* registers.
R/W# indicates read or write operation on the interface. Interface protocol specific (i.e. Async or
Sync, SRAM or ADMux) signals are not shown.