Cypress EX-USB FX3, Руководство программиста

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FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 107
FX3 Serial Peripheral Register Access
3 TX_DONE W R 0
Indicates no more data is available for transmis-
sion. Non sticky.
If DMA_MODE = 0, this is defined as TX FIFO
empty and shift register empty.
If DMA_MODE = 1, this is defined as
BYTES_TARNSFERRED=BYTE_COUNT and
shift register empty.
Note that this field will only assert after a trans-
mission was started - its power up state is 0.
4 TX_SPACE W R 1
Indicates space is available in the TX FIFO.
This bit is updated immediately after writes to
EGRESS_DATA register. Non sticky.
5 TX_HALF W R 1
Indicates that the TX FIFO is at least half empty.
This bit is updated immediately after writes to
EGRESS_DATA register. Non sticky.
6 TIMEOUT RW1S RW1C 0 An I2C bus timeout occurred. Sticky
7
LOST_ARBITR
ATION
RW1S RW1C 0
Master lost arbitration during command. Firm-
ware is responsible for resetting socket (in
DMA_MODE) and re-issuing the command.
Sticky
8 ERROR RW1S RW1C 0
An internal error has occurred with cause
ERROR_CODE. Must be cleared by software.
Sticky
27:24 ERROR_CODE W R 0xF
Error code, only relevant when ERROR = 1.
This only logs the FIRST error to occur and will
never change value as long as ERROR = 1.
0 - 7: Slave NAK-ed the corresponding byte in
the preamble.
8: Slave NAK-ed during data phase.
9: Preamble Repeat exited due to NACK or
ACK.
10: Preamble repeat-count reached without sat-
isfying exit conditions.
11: TX Underflow
12: TX FIFO overflow
13: RX FIFO underflow
14: RX Overflow
15: No error
28 BUSY W R 0
Indicates the block is busy transmitting data.
This field may remain asserted after the block is
suspended and must be polled before changing
any configuration values.
29 BUS_BUSY W R 0
Asserts when the block has detected that it can-
not start an operation (TX/RX) since the bus is
kept busy by another master. De-asserts and
resets when a stop condition is detected or
when the block is disabled.
30 SCL_STAT W R 0 Current status of the SCL line.
31 SDA_STAT W R 0 Current status of the SDA line.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description