Cypress EX-USB FX3, Руководство программиста

Страница: 114 / 192

114 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9:8 STOP_BITS R RW 0
00: Reserved
01: 1 Stop bit.
10: 2 Stop bits
11: Reserved
Note: STOP_BITS = 2 is supported only when
PARITY=0. Behavior is undefined otherwise.
10 DMA_MODE R RW 0
0: Register-based transfers
1: DMA-based transfers
12 RTS R RW 1
Request To Send bit.
Can be used to perform software flow control
when HW flow control is disabled.
Setting this bit to 1 would signal the transmitter
that we are ready to receive data.
Modify only when ENABLE = 0.
13
TX_FLOW_CTRL_
ENBL
R RW 0 1: Enable HW flow control for TX data
14
RX_FLOW_CTRL_
ENBL
R RW 0 1: Enable HW flow control for RX data
15 TX_BREAK R RW 0
0: Default Behavior
1: Wait for the currently transmitting byte to
complete (including the stop bit) and then
transmit 0s indefinitely until this bit is cleared.
Do not transmit other bytes or discard any data
while BREAK is being transmitted.
19:16 RX_POLL R RW 0
Set timing when to sample for RX input:
0: Sample on bits 0,1,2
1: Sample on bits 1,2,3
2: Sample on bits 2,3,4
3: Sample on bits 3,4,5
4: Sample on bits 4,5,6
5: Sample on bits 5,6,7
29 RX_CLEAR R RW 0
0: Do nothing
1: Clear receive FIFO
Firmware must wait for RX_DATA = 0 before
clearing this bit again.
30 TX_CLEAR R RW 0
0: Do nothing
1: Clear transmit FIFO
Firmware must wait for TX_DONE = 1 before
clearing this bit again.
31 ENABLE R RW 0
Enable block here, but only after all of the con-
figuration is set.
Setting this bit to 0 completes transmission of
current sample. When DMA_MODE = 1 any
remaining samples in the pipeline are dis-
carded. When DMA_MODE = 0 no samples
are lost.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description