Cypress EX-USB FX3, Руководство программиста

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40 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Overview
As explained earlier, the CPU accesses the System Memory (Sysmem) using the System AHB and
the DMA paths of the peripherals are all hooked up to the DMA AHB. Bridge(s) between the System
bus and the DMA bus are essential in routing the DMA traffic through the Sysmem.
The following figure illustrates a typical arrangement of the major DMA components of any DMA
capable peripheral of FX3.
Figure 3-13. DMA Components
The figure shows a partition of any FX3 peripheral from a DMA view point. Any FX3 peripheral can
be split into three main components - DMA adapter, thread controller, and peripheral core. The
peripheral attaches to the DMA fabric using AHB, width of which determines the throughput of the
peripheral. The peripheral core implements the actual logic of the peripheral (I
2
C, GPIF, and USB).
Data transfers between the peripheral core and the external world is shown to happen over two
buses - address and data. These buses symbolize that the peripherals of FX3 do not present
themselves as a single large source or sink for data; rather the external host (or device) gets to index
the data to/from different addresses.
In practice though, physical address and data buses may not exist for all peripherals. Each
peripheral has its own interface to communicate addresses and data. For example, all information
exchanges in the USB block happen over the D+ and D– lines. The core logic extracts the address
from the token packet and data from the data packet. The I
2
C interface exchanges all information
over the SDA lines synchronized to a clock on the SCL line. The GPIF interface on the other hand
can be configured to interface using a separate physical address and data bus.
The address specified by the external host (or device) is used to index data from/into one of the
many entities called 'Sockets' which logically present themselves, at the interface, as a chain of
buffers. The buffer chains themselves can be constructed in one of a several possible ways
depending on the application.
PERIPHERAL_AHB
TH0
TH1
TH2
TH3
SCK0
SCK1
SCK2
SCK32
THR_SCK_MAP
settings (FW or fixed)
Peripheral Core Thread controller DMA Adapter
DATA
ADDR
PERIPHERAL_N
L
O
G
I
C
FX3
External
Host or
device