Crystal Vision
Data packet management
TANDEM-300 User Manual R1.2
17
14/02/2008
SMPTE embedding formats are more robust than SONY, and SMPTE1 and SMPTE2 are
a relatively tight compromise on robustness where speed of turn round (embed + de-
embed) is very important. The SMPTE4 setting is very robust and can withstand the
highest levels of data corruption. SMPTE3 is a good compromise between speed and
robustness.
De-embed ALL is the most robust of any de-embed settings, and should always be
selected whenever speed of emb de-embedding is not critical. Even that turn
round time is relatively short and is unlikely to have adverse effect on the relative timing
of audio to video signals.
It is NOT recommended to change from a lower setting to a faster setting whilst ‘on-air’,
as there may be a momentary corruption of audio briefly just after the change. This
particularly applies to SONY1 and SONY2 de-embedding, and to some degree to
SONY1, SONY2, SMPTE1 and SMPTE2 embedding. Other functions or selections are
more robust and unlikely to result in momentary loss of audio data, but selection changes
should really be applied whilst off-air.
Measuring process delay
Practical measurement of the processing delays associated with the available embedding
and de-embedding formats has been done by configuring one side as an embedder and
feeding the embedded data into the other side configured as a de-embedder.
The following table compares minimum mul de-multiplex transport (or embed +
de-embed turn round) times with the SDI PLL set to OFF for digital and analogue I/O:
Example mode combination
Digital delay
DIP2>DOP2
Analog delay
AIP2>AOP2
SONY1 embed + SONY1 de-embed – fastest SONY setting
310µs 1,540µs
SONY4 embed + ALL de-embed – preferred general SONY
setting
830µs 2,070µs
SMPTE1 embed + ALL de-embed – fastest SMPTE setting
670µs 1,900µs
SMPTE4 embed + ALL de-embed – preferred general
SMPTE setting
835µs 2,075µs
Note:
Actual times may vary with Mode and other selections.
Changing DPI2+DOP2 to AIP2+AOP2 adds approximately 1,240µs.
SDI in to SDI out is 1.481µs (400 clock cycles at 270 MHz) with SDI PLL set to OFF.
Selecting PLL ON will add a variable amount of delay between 0.6 and 8.9
microseconds, dependent on the severity of jitter and wander of the incoming 270 Mb/s
SDI clock rate.
