6-12 Memory Configuration and BIOS Settings
SDRAM CAS
Latency Time
Sets the CAS latency time to HCLKS of 2 or 3.
The value for this setting should have been
selected already based on the specifications of the
installed DRAM. Do not change it unless the
specifications of the installed DRAM or the CPU
have changed.
DRAM Data Integrity
Mode
Allows the user to set DRAM Data Integrity
mode to ECC (Error Checking and Correcting) or
Non-ECC. The ECC setting allows detection of
single-bit and multiple-bit errors, and recovery of
single-bit errors. The Non-ECC setting enables
byte-wide write capability but has no provision
for protecting data integrity in the DRAM array.
System BIOS
Cacheable
Allows the user to specify the system BIOS
F000h-F7FFFh area as cacheable or
non-cacheable. The Enabled setting yield better
performance but poses the danger of system
errors if programs are written to this memory
area.
Video BIOS
Cacheable
Allows the user to specify the system BIOS
C000h-F7FFFh area as cacheable or
non-cacheable. The Enabled setting yield better
performance but poses the danger of system
errors if programs are written to this memory
area.
Video RAM
Cacheable
This is a new cache technology for the CPU’s
video memory. By caching the display data, the
display speed can be greatly improved. However,
if your display card cannot support this feature,
you must disable this item. Otherwise, your
system may not boot up.
8 Bit I/O Recovery
Time
This is the length of time, measured in CPU
clocks, which the system will delay after the
completion of an 8 bit input/output (I/O) request.
This delay is necessary for the CPU to recover
from completing the I/O request. This item
allows you to specify the amount of recovery time
allowed for 8 bit I/O. The setting can be NA, or 1
to 8 CPU clocks.
Table 6-6: The Chipset Features Setup Screen items.
Item
Description
Содержание Blaster PC M001
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Страница 14: ...The M001 Motherboard 1 5 Figure 1 1 The M001 motherboard...
Страница 67: ...Printed in Singapore...