4. BIOS Setup
32
User’s Manual
CPU & PCI Bus Control
Phoenix - AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
Item Help
Menu Level
CPU to PCI Write Buffer
[Enabled]
PCI Master 0 ws Write
[Enabled]
PCI Delay Transaction
[Disabled]
↓→←
:Move Enter:Select +/-/PU/PD:Values F10:Save Esc:Exit F1 General Help
F5: Previous Values F6: Fail-Safe Defaults F7: 0 timized Defaults
↓
Figure 4.8. CPU & PCI Bus Control Window (factory setting)
Description
Choice
CPU to PCI Write Buffer
The default is "Enabled"; you usually do not have
to change this setting.
Disabled
Enabled
PCI Master 0 WS Write
The default is "Enabled"; you usually do not have
to change this setting.
Enabled
Disabled
PCI Delay Transaction
The default is "Disabled"; you usually do not have
to change this setting.
Disabled
Enabled
Memory Hole
The default is "Disabled"; you usually do not have
to change this setting.
Disabled
15M – 16M
System BIOS Cacheable
The default is "Disabled"; you usually do not have
to change this setting.
Disabled
Enabled