CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
47
10.5
Porting V1495 to DT5495
Firmware designs targeted to the V1495 User FPGA can be ported to DT5495 by keeping in mind the following
differences between the two modules:
-
The DT5495 FPGA device is different (Cyclone V versus Cyclone I) and with larger logic resources. While there will
be no resource constrains, the FPGA configuration scheme and output binary files are different for the two
boards.
-
A design that used on-board delay lines with V1495 must be redesigned to consider the new features and
characteristics of the DT5495 GDG.
-
The address map of the V1495 VME FPGA and DT5495 MAIN FPGA have some differences to consider:
o
Registers in V1495 are mapped at 16-bit aligned addresses, while DT5495 features a 32-bit aligned address
map. Register access should always be in 32-bit mode.
o
Common registers with different address:
•
0x800C in V1495
•
0x8200 in DT495
-
The local bus map is the same for V1495 and DT5495. Block transfers are allowed only in the 0x0000-0x0FFF
address interval. The same user data prefetch mechanism is implemented. Local bus register accesses are mapped
to the same 0x1000-0x7FFF address interval.
Note:
The DT5495 does not require the 0x100C local bus address to be reserved for user firmware revision register
with special constraints due to the firmware licensing mechanism. In DT5495, all user registers can be implemented in
the allowed address range without any constraints of functionality or content
-
The flash access register map and protocol are different between the two boards: the specific setting and tools
must be used for each module.
