CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
6
Tab. 5.2: A395A Mezzanine specifications table
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Tab. 5.3: A395B Mezzanine specifications table
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Tab. 5.4: A395C Mezzanine specifications table
...........................................................................................................................18
Tab. 5.5: A395D Mezzanine specifications table
...........................................................................................................................18
Tab. 5.6: A395E Mezzanine specifications table
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Tab. 9.1: DT5495 register address map
..........................................................................................................................................35
Tab. 9.2: ROM Address Map of the DT5495
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Tab. 9.3: CSR registers
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Tab. 10.1: Clock ports description table
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Tab. 10.2: Mainboard Robinson-Nugent connector description table
.........................................................................................39
Tab. 10.3: LEMO G ports description table
.....................................................................................................................................39
Tab. 10.4: Expansion I/O ports description table
...........................................................................................................................39
Tab. 10.5: A395D mapping
................................................................................................................................................................40
Tab. 10.6: LED ports description table
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Tab. 10.7: Gate and Delay Generator ports description table
......................................................................................................40
Tab. 10.8: Local Bus ports description table
...................................................................................................................................41
Tab. 10.9: Main parameters of the Gate and Delay Generator
....................................................................................................44
Tab. 10.10: Local Bus registers description for the Gate and Delay Generator configuration
................................................45