CAEN
Electronic Instrumentation
UM6508
–
DT5495 User Manual rev. 0
39
10.2
User FPGA I/O ports
This section illustrates the I/O ports of the UFPGA. Port names are the same of the VHDL entity top-level ports used in
the template and demo firmware.
➢
Clock:
The user FPGA receives the board system clock
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
CLK
1
Input
50 MHz system clock
Tab. 10.1:
Clock ports description table
➢
Mainboard Robinson Nugent connector ports:
the ports A and B are input only. They feature 32 input channels that
reach the UFPGA as 32 single-ended LVTTL lines (3.3 V).
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
A
32
Input
A-port values
B
32
Input
B-port values
C
32
Output C-port value
Tab. 10.2:
Mainboard Robinson-Nugent connector description table
➢
LEMO ports:
each of the LEMOs on the front panel can be used as input or output. The signals used are the
following:
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
GIN
2
Input
Input values for G0, G1
GOUT
2
Output Output values for G0, G1
SELG
Output
NIM/TTL selector
0 = NIM
1 = TTL
nOEG
Output Output enable (active low) (0=output, 1=input)
Tab. 10.3:
LEMO G ports description table
➢
Expansion I/O ports
: for each mezzanine,
Tab. 10.4
shows the supported signals (X = D, E, F).
SIGNAL NAME
WIDTH
TYPE
DESCRIPTION
IDx
3
Input
Card ID
“000” = A395A
“001” = A395B
“010” = A395C
“011” = A395D
“100” = A395E
“111” = No mezzanine present
SELx
1
Output
NIM/TTL selector
0 = NIM
1 = TTL
nOEx
1
Output
Output enable (active low)
0 = output
1 = input
X
32
Input/Output Data bus to/from the mezzanines
Tab. 10.4: Expansion I/O ports description table
Please note that:
•
The SELx and nOEx signals are meaningful only for the A395D mezzanine card. When this mezzanine is not used,
these signals can be left undriven.
•
Mezzanines with 32 I/O signals have a one-to-one correspondence between physical signals and I/O pins (i.e.
X[i] corresponds to the i-th channel of the mezzanine).
