Bull Cedoc Novascale R422, Инструкция по установке и эксплуатации

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NovaScale R422 Installation and User's Guide
Onboard I/O
Four SATA2 ports (supporting RAID0, 1, 10 and 5)
One SIMSO IPMI slot
One Intel Gigabit Ethernet 82563EB controller supports two Giga-bit LAN ports
One COM port
Up to four USB 2.0 (Universal Serial Bus) (2 ports, 2 Headers)
ATI ES1000 Graphic Controller with 16MB Video Memory
Super I/O: Winbond W83627HF
Mellanox MT25204A0-FCC-D In
fi niBand Controller supports one In fi niBand connector
(Only on Novascale R422-INF (X7DBT-INF) motherboard)
Other
External modem ring-on
Wake-on-LAN (WOL)
Wake-on-Ring (WOR)
Console redirection
Onboard Fan Speed Control by Thermal Management via BIOS
Dimensions
Proprietary 16.0" x 6.5" (406.4 mm x 165.1 mm)
Chipset Overview
The Intel 5000P Chipset (for the X7DBT/X7DBT-INF) is built upon the functionality and
the capability of the 5000P chipset, the X7DBT/X7DBT-INF motherboard provides the
performance and feature set required for dual processor-based servers with con fi guration
options optimized for communications, presentation, storage, computation or database
applications. The 5000P chipset supports single or dual Xeon 64-bit dual core processor(s)
with front side bus speeds of up to 1.333 GHz. The chipset consists of the 5000P Memory
Controller Hub (MCH) and the Enterprise South Bridge 2 (ESB2).
The 5000P MCH chipset is designed for symmetric multiprocessing across two independent
front side bus interfaces. Each front side bus uses a 64-bit wide, 1333 MHz data bus
that transfers data at 10.7 GB/sec. The MCH chipset connects up to eight Fully Buffered
DIMM modules, providing a total memory of up to 32.0 GB for DDR2 667/533 MHz.
The MCH chipset also provides one x8 PCI-Express and one x4 ESI interfaces to the ESB2.
In addition, the 5000P chipset offers a wide range of RAS features, including memory
interface ECC, x4/x8 Single Device Data Correction, CRC, parity protection, memory
mirroring and memory sparing.
The Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000P chipset, the Xeon dual core Processor
provides a feature set as follows:
L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
L2 Cache Size: 4MB/2MB (per core)
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