CHAPTER 2 THEORY OF OPERATION
Confidential
2-4
2.3 Main
PCB
For the entire circuit diagram of the main PCB.
2.3.1 CPU
A Sapphire – 266 MHz (Vr5500) is built into the CPU in the ASIC. It runs at a clock frequency
of 266 MHz.
The functions of the interface block communication with external devices are described below;
2.3.2 USB interface (2.0 High Speed)
Stores the data received from the PC into DRAM as controlled by the DMA controller. The
transmission speed is 12Mbps.
2.3.3 IEEE1284
interface
Stores the data received from the PC into DRAM by DMA using the Gate Array
(UPD65421MC-11) exclusive for parallel I/F. It is for the normal reception and dual direction
communication (nibble mode, byte mode, ECP mode).
2.3.4 Network
interface
It uses the National Semiconductor brand 10 Base-T/100 Base-TX network controller
(LAN9115). The pulse transformer and the Link/Active LED are built in the RJ-45 connector.
2.3.5 ROM
< ROM 0 >
64 Mbit ROM (8 MB) is fitted.
The main program is written into the ROM.
< ROM 1: Demo Specification For US, Canada>
16 Mbit ROM (2 MB) is fitted. (HL-5240)
32 Mbit ROM (4 MB) is fitted. (HL-5250DN)
< ROM 1: Standard Specification >
16 Mbit ROM (2 MB) is fitted. (HL-5250DN)
32 Mbit ROM (4 MB) is fitted. (HL-5270DN/5280DW)
2.3.6 SDRAM
16 MB SDRAM (128 Mbits x 1) is used as the RAM. (HL-5240)
32 MB SDRAM (256 Mbits x 1) is used as the RAM. (HL-5250DN/5270DN/5280DW)
2.3.7 Optional
RAM
1 DIMM (144pin) slot can be fitted as optional expansion RAM. The main PCB has one slot
and the capacity of DIMM can be from 64MB to 512MB.
2.3.8 EEPROM
The EEPROM is M24C16 type of two-wire method with a 16kbit configuration.
