FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
32
Copyright © Bridgetek Limited
3
Register Description
In this chapter, all the registers in the FT800 are classified into 5 groups: Graphics
Engine Registers, Audio Engine Registers, Touch Engine Registers, and Co-processor
Engine Registers as well as Miscellaneous Registers. This chapter gives the detailed
definition for each register. To view the register summary of the FT800, please check the
datasheet instead.
In addition, please note that all the reserved bits are read-only and shall be zero. All the
hexadecimal values are prefixed with 0x. Readers are strongly encouraged to cross-
reference the other chapters of this document for a better understanding.
3.1
Graphics Engine Registers
Register Definition 1
REG_PCLK Definition
31
8 7
0
Address: 0x10246C
Reset Value: 0x0
Note: NONE
REG_PCLK Definition
Bit 0 - 7 : These bits are set to divide the main clock for PCLK. If the typical
main clock was 48MHz and the value of these bits are 5, the PCLK will be 9.6
MHz. If the value of these bits are zero, there will be no PCLK output.
R/W
Reserved