FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
68
Copyright © Bridgetek Limited
3.4
Co-processor Engine Registers
Register Definition 54
REG_CMD_DL Definition
31
14 13
0
REG_CMD_DL Definition
Address: 0x1024EC
Reset Value: 0x0000
Note: .
R/W
Reserved
Bit 0 - 13 : These bits indicate the offset from RAM_DL of a display list command
generated by the coprocessor engine. The coprocessor engine depends on these
bits to determine the address in the display list buffer of generated display list
commands. The coprocessor engine will update this register as long as the display
list commands are generated into the display list buffer. By setting this register
properly, the host can specify the starting address in the display list buffer for the
coprocessor engine to generate display commands. The valid value range is from 0
to 8195.
Register Definition 55
REG_CMD_WRITE Definition
Address: 0x1024E8
Reset Value: 0x0
Note: FIFO size of command buffer is 4096 bytes and each co-processor
instruction is of 4 bytes in size. The value to be written into this register must
be 4 bytes aligned.
Bit 0 - 11 : These bits are updated by the host MCU to inform the coprocessor
engine of the ending address of valid data feeding into its FIFO. Typically, the
host will update this register after it has downloaded the coprocessor
commands into its FIFO. The valid range is from 0 to 4095, i.e. within the size
of the FIFO.