FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
145
Copyright © Bridgetek Limited
The co-processor engine is fed via a 4 Kbyte FIFO in FT800 memory at RAM_CMD. The
MCU writes commands into the FIFO, and the co-processor engine reads and executes
the commands. The MCU updates register REG_CMD_WRITE to indicate that there are
new commands in the FIFO, and the co-processor engine updates REG_CMD_READ after
commands have been executed.
So to compute the available free space in the FIFO, the MCU can compute:
fullness
= (REG_CMD_WRITE -REG_CMD_READ)
mod
4096
freespace
= (4096 - 4) -
fullness
;
This calculation does not report 4096 bytes of free space, to prevent completely
wrapping the FIFO and making it appear empty.
If enough space is available in the FIFO, the MCU writes the commands at the
appropriate location in the FIFO RAM, then updates REG_CMD_WRITE. To simplify the
MCU code, the FT800 hardware automatically wraps continuous writes from (RAM_CMD
+ 4095) back to (R 0).
FIFO entries are always 4 bytes wide - it is an error for either REG_CMD_READ or
REG_CMD_WRITE to have a value that is not a multiple of 4 bytes. Each command
issued to the co-processor engine may take 1 or more words: the length depends on the
command itself, and any appended data. Some commands are followed by variable-
length data, so the command size may not be a multiple of 4 bytes. In this case the co-
processor engine ignores the extra 1, 2 or 3 bytes and continues reading the next
command at the following 4 byte boundary.
