FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
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Copyright © Bridgetek Limited
REG_VCYCLE
REG_VOFFSET
REG_VSIZE
REG_VSYNC0
REG_VSYNC1
And the REG_CSPREAD register changes color clock timing to reduce system noise.
GPIO bit 7 is used for the display enable pin of the LCD module. By setting the direction
of the GPIO bit to out direction, the display can be enabled by writing value of 1 into
GPIO bit 7 or the display can be disabled by writing a value of 0 into GPIO bit 7. By
default GPIO bit 7 direction is output and the value is 0.
Note: Refer to FT800 data sheet for information on display register set.
2.2.1
Horizontal timing
Figure 2: Horizontal Timing
REG_PCLK controls the frequency of PCLK. The register specifies a divisor for the main
48 MHz clock, so a value of 4 gives a 12 MHz PCLK. If REG_PCLK is zero, then all display
output is suspended. REG_PCLK_POL controls the polarity of PCLK. Zero means that
display data is clocked out on the rising edge of PCLK. One means data is clocked on the
falling edge.
The total number of PCLKs in a horizontal line is REG_HCYCLE. Within this horizontal line
are the scanned out pixels, REG_HSIZE in total. They start after REG_HOFFSET cycles.
Signal DE is high while pixels are being scanned out.
Horizontal sync timing on signal HSYNC is controlled by REG_HSYNC0 and REG_HSYNC1.
They specify the time at which HSYNC falls and rises respectively.