FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
16
Copyright © Bridgetek Limited
2.2.5
Initialization Sequence
This section describes the initialization sequence in the different scenario.
Initialization Sequence during the boot up:
1.
Use MCU SPI clock not more than 11MHz
2.
Send Host command “CLKEXT” to FT800
3.
Send Host command “ACTIVE” to enable clock to FT800.
4.
Configure video timing registers, except REG_PCLK
5.
Write first display list
6.
Write REG_DLSWAP, FT800 swaps display list immediately
7.
Enable back light control for display
8.
Write REG_PCLK, video output begins with the first display list
9.
Use MCU SPI clock not more than 30MHz
MCU_SPI_CLK_Freq
(<
11MHz
);
//use the MCU SPI clock less than 11MHz
host_command
(
CLKEXT
);
//send command to "CLKEXT" to FT800
host_command
(
ACTIVE
);
//send host command "ACTIVE" to FT800
/* Configure display registers - demonstration for WQVGA resolution */
wr16
(
REG_HCYCLE
,
548
);
wr16
(
REG_HOFFSET
,
43
);
wr16
(
REG_HSYNC0
,
0
);
wr16
(
REG_HSYNC1
,
41
);
wr16
(
REG_VCYCLE
,
292
);
wr16
(
REG_VOFFSET
,
12
);
wr16
(
REG_VSYNC0
,
0
);
wr16
(
REG_VSYNC1
,
10
);
wr8
(
REG_SWIZZLE
,
0
);
wr8
(
REG_PCLK_POL
,
1
);
wr8
(
REG_CSPREAD
,
1
);
wr16
(
REG_HSIZE
,
480
);
wr16
(
REG_VSIZE
,
272
);
/* write first display list */
wr32
(
RAM_DL
+
0
,
CLEAR_COLOR_RGB
(
0
,
0
,
0
));
wr32
(
RAM_DL
+
4
,
CLEAR
(
1
,
1
,
1
));
wr32
(
RAM_DL
+
8
,
DISPLAY
());
wr8
(
REG_DLSWAP
,
DLSWAP_FRAME
);
//display list swap
wr8
(
REG_GPIO_DIR
,
0x80
|
Ft_Gpu_Hal_Rd8
(
phost
,
REG_GPIO_DIR
));
wr8
(
REG_GPIO
,
0x080
|
Ft_Gpu_Hal_Rd8
(
phost
,
REG_GPIO
));
//enable display bit
wr8
(
REG_PCLK
,
5
);
//after this display is visible on the LCD
MCU_SPI_CLK_Freq
(<
30Mhz
);
//use the MCU SPI clock upto 30MHz
Code snippet 1 Initialization sequence
Initialization Sequence from Power Down using PD_N pin: