FT800 Series Programmer Guide
Version 2.1
Document Reference No.: BRT_000030 Clearance No.: BRT#037
44
Copyright © Bridgetek Limited
Register Definition 20
REG_DLSWAP Definition
Reserved
31
2 1
0
Address: 0x102450
Reset Value: 0x00
REG_DLSWAP Definition
Note:
R/W
Bi t 0 - 1: These bi ts can be set by the host to val i date the di spl ay l i st buffer
of the FT800. The FT800 graphi cs engi ne wi l l determi ne when to render the
screen , dependi ng on what val ues of these bi ts are set:
01: Graphi cs engi ne wi l l render the screen i mmedi atel y after current l i ne
i s scanned out. It may cause teari ng effect.
10: Graphi cs engi ne wi l l render the screen i mmedi atel y after current
frame i s scanned out. Thi s i s recommended i n most of cases.
00: Do not wri te thi s val ue i nto thi s regi ster.
11: Do not wri te thi s val ue i nto thi s regi ster.
These bi ts can be al so be read by the host to check the avai l abi l i ty of the
di spl ay l i st buffer of the FT800. If the val ue i s read as zero, the di spl ay l i st
buffer of the FT800 i s safe and ready to wri te. Otherwi se, the host needs to
wai t ti l l i t becomes zero.