AT32WB415
Series Reference Manual
2022.04.13
Page 48
Ver 2.00
The LEXT crystal/ceramic resonator provides a 32.768 KHz low-speed clock source. The LEXT clock
signal is not released before it becomes stable.
LEXT bypass clock:
In this mode, an external clock source with a frequency of 32.768 kHzcan be provided. The external
clock signal should be connected to the LEXT_IN pin while the LEXT_OUT can be released for GPI
control.
Low speed internal RC oscillator (LICK)
The LICK oscillator is clocked by an internal low-speed RC oscillator. The clock frequency is between
30 kHz and 60 kHz. It acts as a low-power clock source that can be kept running in Deepsleep mode
and Standby mode for watchdog and auto-wakeup unit.
The LICK clock signal is not released before it becomes stable.
4.1.2
System clock
After a system reset, the HICK oscillator is selected as system clock. The system clock can make flexible
switch among HICK oscillator, HEXT oscillator and PLL clock. However, a switch from one clock source
to another occurs only when the target clock source becomes stable. When the HICK oscillator is used
directly or indirectly through the PLL as the system clock, it cannot be stopped.
4.1.3
Peripheral clock
Most peripherals use HCLK, PCLK1 or PCLK2 clock. The individual peripherals have their dedicated
clocks.
System Tick timer (SysTick) is clocked by HCLK or HCLK/8.
ADC is clocked by APB2 divided by 2, 4, 6, 8, 12, 16.
The timers are clocked by APB1/2. In particular, if the APB prescaler is 1, the timer clock frequency is
equal to that of APB1/2; otherwise, the timer clock frequency doubles that of the APB1/2 frequency.
A frequency-divided PLL clock can be used as the clock source of USB. If the PLL frequency divider is
selected, the USB frequency divider provides a 48 MHz USBCLK, and thus the PLL must be set as
48*N*0.5 MHz (N=2,3,4,5…)
ERTC clock sources: HEXT/128 oscillator, LEXT oscillator and LICK oscillator. Once the clock source is
selected, it cannot be altered without resetting the battery powered domain. If the LEXT is used as an
ERTC clock, the ERTC is not affected when the VDD is powered off. If the HEXT or LICK is selected as
an ERTC clock, the ERTC state is not guaranteed when both HEXT and LICK are powered off.
Watchdog is clocked by LICK oscillator. If the watchdog is enabled by either hardware option or software
access, the LICK oscillator is forced ON. The clock is provided to the watchdog only after the LICK
oscillator temporization.
4.1.4
Clock fail detector
The clock fail detector (CFD) is designed to respond to HEXT clock failure when the HEXT is used as a
system clock ,directly or indirectly. If a failure is detected on the HEXT clock, a clock failure event is sent
to the break input of TMR1 and an interrupt is generated. This interrrpt is directly linked to CPU NMI so
that the software can perform rescue operations. The NMI interrupt keeps executing until the CFD
interrupt pending bit is cleared. This is why the CFD interrupt has to be cleared in the NMI service rounte.
The HEXT clock failure will result in a switch of the system clock to the HICK clock, the CFD to be
disabled , HEXT clock to be stopped, and even PLL to be disabled if the HEXT clock is selected as the
system clock through PLL.
4.1.5
Auto step-by-step system clock switch
The automatic frequency switch is designed to ensure a smooth and stable switch of system frequency
when the system clock source is switched from others to the PLL or when the AHB prescaler is changed
from large to small. When the operational target is larger than 108 MHz, it is recommended to enable
the automatic frequency switch. Once it is enabled, the AHB bus is halted by hardware till the completion
of the switch. During this switch period, the DMA remain working, and the interrupt events are recorded
and then handled by NVIC when the AHB bus resumes.
