AT32WB415
Series Reference Manual
2022.04.13
Page 143
Ver 2.00
12.11 USART registers
These peripheral registers must be accessed by words (32 bits).
Table 12-4
USART register map and reset value
Register
Offset
Reset value
USART_STS
0x00
0x0000 00C0
USART_DT
0x04
0x0000 0000
USART_BAUDR
0x08
0x0000 0000
USART_CTRL1
0x0C
0x0000 0000
USART_CTRL2
0x10
0x0000 0000
USART_CTRL3
0x14
0x0000 0000
USART_GDIV
0x18
0x0000 0000
12.11.1 Status register (USART_STS)
Bit
Register
Reset value
Type
Description
Bit 31: 10 Reserved
0x000000
resd
Forced 0 by hardware.
Bit 9
CTSCF
0x0
rw0c
CTS change flag
This bit is set by hardware when the CTS status line
changes. It is cleared by software.
0: No change on the CTS status line
1: A change occurs on the CTS status line.
Bit 8
BFF
0x0
rw0c
Break frame flag
This bit is set by hardware when a break frame is detected.
It is cleared by software.
0: Break frame is not detected.
1: Break frame is detected.
Bit 7
TDBE
0x1
ro
Transmit data buffer empty
This bit is set by hardware when the transmit data buffer is
empty. It is cleared by a USART_DT register write
operation.
0: Data is not transferred to the shift register.
1: Data is transferred to the shift register.
Bit 6
TDC
0x1
rw0c
Transmit data complete
This bit is set by hardware at the end of transmission. It is
cleared by software. (Option 1: read access to
USART_STS register followed by a USART_DT write
operation; Option 2: Write “0” to this bit )
0: Transmission is not completed.
1: Transmission is completed.
Bit 5
RDBF
0x0
rw0c
Receive data buffer full
This bit is set by hardware when the data is transferred
from the shift register to the USART_DT register. It is
cleared by software. (Option 1: read USART_DT register;
Option 2: write “0” to this bit)
0: Data is not received.
1: Data is received.
Bit 4
IDLEF
0x0
ro
Idle flag
This bit is set by hardware when an idle line is detected. It
is cleared by software. (Read USART_DT register followed
by a USART_DT read operation)
0: No idle line is detected.
1: Idle line is detected.
Bit 3
ROERR
0x0
ro
Receiver overflow error
This bit is set by hardware when the data is received while
the RDNE is still set. It is cleared by software. (Read
USART_STS register followed by a USART_DT read
operation)
0: No overflow error