
AT32WB415
Series Reference Manual
2022.04.13
Page 356
Ver 2.00
handshakes on an endpoint. The controller sets this bit on
a Transfer completed interrupt or after receiving a SETUP
packet.
Values:
0: Do not set NAK
1: Set NAK
Bit 26
CNAK
0x0
wo
Clear NAK
A write to this bit clears the NAK bit for this endpoint.
0: Not clear NAK
1: Clear NAK
Bit 25: 22 TXFNUM
0x0
rw
TxFIFO number
Allocate FIFO number to the corresponding endpoint. A
separate FIFO number is allocated to each valid IN
endpoint. This bit applies to IN endpoints only.
Bit 21
STALL
0x0
rw
STALL handshake
Applies to non-control, non-synchronous IN and OUT
endpoints.
The application sets this bit to stall all tokens from the USB
host to this endpoint. If a NAK bit , glocal non-periodic IN
NAK bit or global OUT NAK bit is set along with this bit, the
STALL bit has priority. Only the application can clear this
bit, but the controller never.
0: Stall all invalid tokens
1: Stall all valid tokens
Bit 20
Reserved
0x0
resd
Kept at its default value.
Bit 19: 18 EPTYPE
0x0
rw
Endpoint type
This is the transfer type supported by this logical endpoint.
00: Control
01: Synchronous
10: Bulk
11: Interrupt
Bit 17
NAKSTS
0x0
ro
NAK status
Indicates the following status:
0: The controller is sending non-NAK handshakes based
on the FIFO status
1: The controller is sending NAK handshakes
–
When this bit is set (either by the application or the
controller), the controller stops receiving any data on an
OUT endpoint, even if there is space in the receive FIFO
to accommodate the incoming data packets.
–
For non-synchronous IN endpoints: the controller stops
transmitting data on the endpoint, even if there is data
pending in the transmit FIFO.
–
For synchronous IN endpints: the controller sends a zero-
length data packet, even if there is space in the transmit
FIFO.
The controller always responds to SETUP data packets
with an ACK handshake, regardless of whether this bit is
set or not.
Bit 16
DPID/
EOFRNUM
0x0
ro
Endpoint data PID
Applies to interrupt/bulk IN endpoints only.
This bit contains the PID of the packet to be transmitted on
this endpoint. The application must program the PID of the
initial data packet to be received or transmitted on this
endpoint, after the endpoing is enabled. The application
programs DATA0 or DATA1 PID through the SetD1PID and
SetD0PID of this register.
0: DATA0
1: DATA1
Even/Odd frame
Applies to synchronous IN endpoints only.
Indicates the frame number in which the controller
transmits synchronous data on this endpoint. The
application must program the even/odd frame number in
which it tends to transmit or receive synchronous data