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AT32WB415
Series Reference Manual
2022.04.13
Page 283
Ver 2.00
Note:
This bit is set by hardware when three messages are
pending in the FIFO 1.
It is cleared by software by writing 1.
Bit 2
Reserved
0x0
resd
Kept at its default value.
Bit 1: 0
RF1MN
0x0
ro
Receive FIFO 1 message num
Note:
These two bits indicate how many messages are pending
in the FIFO 1.
RF1ML bit is incremented by one each time a new
message has been received and passed the fitler while the
FIFO 1 is not full.
RF1ML bit is decremented by one each time the software
releases the receive FIFO 1 by writing 1 to the RF1R bit.
19.7.1.6 CAN interrupt enable register (CAN_INTEN)
Bit
Register
Reset value
Type
Description
Bit 31: 18 Reserved
0x0000
resd
Kept at its default value.
Bit 17
EDZIEN
0x0
rw
Enter doze mode interrupt enable
0: Enter sleep mode interrupt disabled
1: Enter sleep mode interrupt enabled
Note: EDZIF flag bit corresponds to this interrupt. An
interrupt is generated when both this bit and EDZIF bit are
set.
Bit 16
QDZIEN
0x0
rw
Quit doze mode interrupt enable
0: Quit sleep mode interrupt disabled
1: Quit sleep mode interrupt enabled
Note: The flag bit of this interrupt is the QDZIF bit. An
interrupt is generated when both this bit and QDZIF bit are
set.
Bit 15
EOIEN
0x0
rw
Error occur interrupt enable
0: Error interrupt disabled
1: Error interrupt enabled
Note:The flag bit of this interrupt is the EOIF bit. An
interrupt is generated when both this bit and EOIF bit are
set.
Bit 14: 12 Reserved
0x0
resd
Kept at its default value.
Bit 11
ETRIEN
0x0
rw
Error type record interrupt enable
0: Error type record interrupt disabled
1: Error type record interrupt enabled
Note: EOIF is set only when this interrupt is enabled and
the ETR[2: 0] is set by hardware.
Bit 10
BOIEN
0x0
rw
Bus-off interrupt enable
0: Bus-off interrupt disabled
1: Bus-off interrupt enabled
Note: EOIF is set only when this interrupt is enabled and
the BOF is set by hardware.
Bit 9
EPIEN
0x0
rw
Error passive interrupt enable
0: Error passive interrupt disabled
1: Error passive interrupt enabled
Note: EOIF is set only when this interrupt is enabled and
the EPF is set by hardware.
Bit 8
EAIEN
0x0
rw
Error active interrupt enable
0: Error warning interrupt disabled
1: Error warning interrupt enabled
Note: EOIF is set only when this interrupt is enabled and
the EAF is set by hardware.
Bit 7
Reserved
0x0
resd
Kept at its default value.
Bit 6
RF1OIEN
0x0
rw
Receive FIFO 1 overflow interrupt enable
0: Receive FIFO 1 overflow interrupt disabled
1: Receive FIFO 1 overflow interrupt enabled
Note: The flag bit of this interrupt is the RF1OF bit. An
interrupt is generated when this bit and RF1OF bit are set.
Bit 5
RF1FIEN
0x0
rw
Receive FIFO 1 full interrupt enable