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AT32WB415
Series Reference Manual
2022.04.13
Page 284
Ver 2.00
0: Receive FIFO 1 full interrupt disabled
1: Receive FIFO 1 full interrupt enabled
Note: The flag bit of this interrupt is the RF1FF bit. An
interrupt is generated when this bit and RF1FF bit are set.
Bit 4
RF1MIEN
0x0
rw
FIFO 1 receive message interrupt enable
0: FIFO 1 receive message interrupt disabled
1: FIFO 1 receive message interrupt enabled
Note: The flag bit of this interrupt is RF1MN bit, so an
interrupt is generated when this bit and RF1MN bit are set.
Bit 3
RF0OIEN
0x0
rw
Receive FIFO 0 overflow interrupt enable
0: Receive FIFO 0 overflow interrupt disabled
1: Receive FIFO 0 overflow interrupt enabled
Note: The flag bit of this interrupt is RF0OF bit, so an
interrupt is generated when this bit and RF0OF bit are set.
Bit 2
RF0FIEN
0x0
rw
Receive FIFO 0 full interrupt enable
0: Receive FIFO 0 full interrupt disabled
1: Receive FIFO 0 full interrupt enabled
Note: The flag bit of this interrupt is the RF0FF bit. An
interrupt is generated when this bit and RF0FF bit are set
Bit 1
RF0MIEN
0x0
rw
FIFO 0 receive message interrupt enable
0: FIFO 0 receive message interrupt disabled
1: FIFO 0 receive message interrupt enabled
Note: The flag bit of this interrupt is the RF0MN bit. An
interrupt is generated when this bit and RF0MN bit are set
Bit 0
TCIEN
0x0
rw
Transmit mailbox empty interrupt enable
0: Transmit mailbox empty interrupt disabled
1: Transmit mailbox empty interrupt enabled
Note: The flag bit of this interrupt is the TMxTCF bit. An
interrupt is generated when this bit and TMxTCF bit are set
19.7.1.7 CAN error status register (CAN_ESTS)
Bit
Register
Reset value
Type
Description
Bit 31: 24 REC
0x00
ro
Receive error counter
This counter is implemented in accordance with the
receive part of the falut confinement mechanism of the
CAN protocol.
Bit 23: 16 TEC
0x00
ro
Transmit error counter
This counter is implemented in accordance with the
transmit part of the falut confinement mechanism of the
CAN protocol.
Bit 15: 7
Reserved
0x00
resd
Kept at its default value.
Bit 6: 4
ETR
0x0
rw
Error type record
000: No error
001: Bit stuffing error
010: Format error
011: Acknowledgement error
100: Recessive bit error
101: Dominant bit error
110: CRC error
111: Set by software
Note:
This field is used to indicate the current error type. It is set
by hardware according to the error condition detected on
the CAN bus. It is cleared by hardware when a message
has been transmitted or received successfully.
If the error code 7 is not used by hardware, this field can
be set by software to monitor the code update.
Bit 3
Reserved
0x0
resd
Kept at its default value.
Bit 2
BOF
0x0
ro
Bus-off flag
0: Bus-off state is not entered.
1: Bus-off state is entered.
Note: When the TEC is greater than 255, the bus-off state
is entered, and this bit is set by hardware.
Bit 1
EPF
0x0
ro
Error passive flag