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ADSP-2126x SHARC Processor Hardware Reference
14-9
Peripheral Timer
0xFFFF FFFF – width. The timer counts upward to 0xFFFF FFF. Instead
of incrementing to 0xFFFF FFFF, the timer then reloads the counter with
the value derived from 0xFFFF FFFF – (period – width) and repeats.
PWM Waveform Generation
If the
PRDCNT
bit is set, the internally-clocked timer generates rectangular
signals with well-defined period and duty cycles. This mode also generates
periodic interrupts for real-time DSP processing.
The 32-bit Period (
TMxPRD
) and Width (
TMxW
) registers are programmed
with the values of the timer count period and pulse width modulated out-
put pulse width.
When the timer is enabled in this mode, the
TIMERx
signal is pulled to a
deasserted state each time the pulse width expires, and the signal is
asserted again when the period expires (or when the timer is started).
To control the assertion sense of the
TIMERx
signal, the
PULSE
bit in the
corresponding
TMxCTL
register is either cleared (causes a low assertion
level) or set (causes a high assertion level).
When enabled, a timer interrupt is generated at the end of each period. An
ISR must clear the Interrupt Latch bit
TIMxIRQ
and might alter period
and/or width values. In pulse width modulation applications, the software
needs to update the period and pulse width values while the timer is
running.
When a program updates the timer configuration, the
TMxW
register must
always be written to last, even if it is necessary to update only one of the
registers. When the
TMxW
value is not subject to change, the ISR reads the
current value of the
TMxW
register and rewrite it again. On the next counter
reload, all of the timer Control registers are read by the timer.
To generate the maximum frequency on the
TIMERx
output signal, set the
period value to two and the pulse width to one. This makes the
TIMERx
signal toggle every two
CCLK
clock cycles.
Содержание ADSP-21261 SHARC
Страница 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Страница 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Страница 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Страница 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Страница 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...