8-8
ADSP-2126x SHARC Processor Hardware Reference
does not show
ALE
cycles; it shows only the order of the
Parallel port DMAs can only be performed to 32-bit (normal word)
internal memory.
Transfer Protocol
The external interface follows the standard asynchronous SRAM access
protocol. The programmable Data Cycle Duration (
PPDUR
) and optional
Bus Hold Cycle (
BHC
) addition at the end of each data cycle are provided
to interface with memories having different access time requirements. The
data cycle duration is programmed via the
PPDUR
bit in the
PPCTL
register.
The hold cycle at the end of the data cycle is programmed via the
PPBHC
bit in the
PPCTL
register.
Disabling the parallel port (
PPEN
bit is cleared) flushes both parallel
port FIFOs,
RXPP
, and
TXPP
.
For standard asynchronous SRAM there are two transfer modes—8-bit
and 16-bit mode. In 8-bit mode, the address range is 0x0 to 0xFFFFFF
which is 16M bytes (4M 32-bit words). In 16-bit mode, the address range
is 0x0 to 0xFFFF which is a 128K bytes (32K 32-bit words). Although
programs can initiate reads or writes on one and two byte boundaries, the
parallel port always transfers 4 bytes (two 16-bit or four 8-bit words).
Table 8-2. Unpacking Sequence for 32-Bit Data
Transfer
AD7–0, 32-bit to 8-bit
(8-bit bus, LSW first)
AD15–0, 32-bit to 16-bit
(16-bit bus, LSW first)
First
Word 1; bits 7–0
Word 1; bits 15–0
Second
Word 1; bits 15–8
Word 1; bits 31–16
Third
Word 1; bits 23–16
Fourth
Word 1; bits 31–24
Содержание ADSP-21261 SHARC
Страница 30: ...Contents xxx ADSP 2126x SHARC Processor Hardware Reference ...
Страница 40: ...Register Diagram Conventions xl ADSP 2126x SHARC Processor Hardware Reference ...
Страница 58: ...Differences From Previous SHARCs 1 18 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 112: ...Secondary Processing Element PEy 2 54 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 178: ...Summary 3 66 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 204: ...DAG Instruction Summary 4 26 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 322: ...Setting Up DMA 7 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 436: ...SPORT Programming Examples 9 86 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 521: ...ADSP 2126x SHARC Processor Hardware Reference 11 31 Input Data Port rts IDP_ISR end ...
Страница 522: ...Input Data Port Programming Example 11 32 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 590: ...Timer Programming Examples 14 20 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 796: ...I O Processor Registers A 174 ADSP 2126x SHARC Processor Hardware Reference ...
Страница 800: ...B 4 ADSP 2126x SHARC Processor Core Manual ...
Страница 846: ...Index I 36 ADSP 2126x SHARC Processor Hardware Reference ...