Analog Devices ADSP-21261 SHARC, Справочник по аппаратуре

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ADSP-2126x SHARC Processor Hardware Reference 5-29
Memory
Instruction Examples
R8 = DM (I4,M3), PM (I12,M13) = R0; /* Dual access */
R0 = DM (I5,M5); / * Single access */
For examples of data flow paths for single and dual-data transfers, see the
following section,
“Internal Memory Access Listings” on page 5-30 .
Shadow Write FIFO
Because the processor’s internal memory operates at high speeds, writes to
the memory block do not go directly into the memory array, but rather to
a two-deep FIFO called the shadow write FIFO. This does not apply to
ROM type block. The four shadow FIFOs are located inside the internal
memory interface block (
Figure 5-1 and Figure 5-2 ) which is responsible
for access control to the individual blocks.
This FIFO uses a non-read cycle (either a write cycle, or a cycle in which
there is no access of internal memory) to load data from the FIFO into
internal memory. When an internal memory write cycle occurs, the FIFO
loads any data from a previous write into memory and accepts new data.
When writing into a memory block, the writes passes through the shadow
write buffer. Note the shadow FIFO is self-clearing, the last two writes are
moved at any point into the block array.
Data can be read from internal memory in either of the following ways.
1. From the shadow write FIFO (caused by immediately read of the
same data after a write).
2. From the memory block.