American Megatrends Olympus III, Руководство пользователя

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Chapter Two : Hardware Installation 51
Step 6 Install Expansion Boards,
Continued
PCI Slots
PCI Slots
PCI 0
PCI 1
PCI 2
PCI 3
PCI 4
The Olympus III incorporates five PCI slots for a various expansion boards. The
Olympus III PCI slots can accept standard 32 bit PCI expansion boards. All of the PCI
bus connectors are bus master capable.
Note: Read the documentation for the expansion board before installing it into the system.
PCI IRQ Routing Table
This section describes interrupt sharing and how the interrupt signals are connected
between the PCI bus connectors and onboard PCI devices. The PCI specification
specifies how interrupts can be shared between devices attached to the PCI bus. In most
cases, the small amount of latency added by interrupt sharing does not affect the
operation or throughput of the devices. In some special cases where maximum
performance is needed from a device, a PCI device should not share an interrupt with
other PCI devices. Use the following information to avoid sharing an interrupt with a PCI
add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
•
INTA: By default, all expansion boards that require only one interrupt are in this
category. For almost all expansion boards that require more than one interrupt,
the first interrupt on the expansion board is also classified as INTA.
•
INTB: Generally, the second interrupt on expansion boards that require two or
more interrupts is classified as INTB. (This is not an absolute requirement.)
•
INTC and INTD: Generally, a third interrupt on expansion boards is classified
as INTC and a fourth interrupt is classified as INTD.
The ICH has eight programmable interrupt request (PIRQ) input signals. All PCI
interrupt sources either onboard or from a PCI expansion board connect to one of these
PIRQ signals. Some PCI interrupt sources are electrically tied together on the Olympus
III motherboard and therefore share the same interrupt. The following table shows an
example of how the PIRQ signals are routed.
Cont’d