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PCI Bus Host Bridge
9-20 Élan™SC520 Microcontroller User’s Manual
The PCI host bridge retries any external PCI bus master write cycle when the write FIFO
is full. The PCI host bridge retries all external PCI bus master cycles (write and read) if the
address FIFO is full (see the Section 9.5.4.5).The PCI host bridge always disconnects after
64 consecutive doublewords are transferred to prevent any one PCI bus master from
monopolizing the bus and to guarantee sufficient CPU bus bandwidth.
9.5.4.5 Address FIFO
The PCI host bridge’s target controller includes an address FIFO that keeps track of address
and command requests made to the target controller. The address FIFO allows one
outstanding delayed read transaction and up to four posted writes, depending on the
ordering of the transactions.
■
If the address FIFO is empty (no latched transactions in the target controller) and a read
transaction is received prior to any posted writes, the read is latched and a delayed
transaction retry is issued. After this, up to four posted writes can be latched following
the read (for a total of five latched transactions in the FIFO).
■
If the address FIFO contains any posted write transaction (before a read transaction is
received), only a total of four transactions can be latched into the address FIFO. That
is, if the first posted transaction is a write, up to four transactions can be latched into the
address FIFO (three writes and one read, or four writes).
■
If four posted writes reside in the address FIFO, no delayed read transactions can be
latched. In this case, all read requests are retried (not latched into the address FIFO)
until one of the posted writes has completed internally.
■ In all cases, only a maximum of one delayed read transaction can be latched into the
address FIFO. If two read transactions are received, the target controller only latches
the first one. The second (and subsequent) reads are not latched into the target
controller, even if the address FIFO is not full.
■ Note that, even if the address FIFO is not full, but the data FIFO is already full, further
posted writes are not accepted.
The ÉlanSC520 microcontroller’s PCI host bridge complies to the PCI Local Bus
Specification, Revision 2.2, rules for transaction ordering to prevent deadlock conditions.
9.5.4.6 PCI Host Bridge FIFOs and Prefetching
The PCI host bridge target controller has a 64-doubleword write FIFO and posts writes from
external PCI bus masters to SDRAM. The PCI host bridge does not insert wait states into
an external PCI bus master write cycle by deasserting TRDY. If the write FIFO becomes
full during an external PCI bus master write transaction, the PCI host bridge issues a
disconnect to end the cycle. A maximum of four transfers can be posted (each transfer can
burst multiple data phases, but the ÉlanSC520 microcontroller’s target FIFOs store a
maximum number of 64 doublewords for all the posted writes).
The SDRAM controller’s write buffer can byte-merge, combine, and collapse data if
enabled, yielding additional performance of SDRAM writes from PCI bus masters. See
Chapter 11, “Write Buffer and Read Buffer”, for further details. However, the PCI host bridge
does
not byte-merge, combine, or collapse data in the target write FIFO.
The PCI host bridge as a target prefetches data from SDRAM in response to an external
PCI bus master read transaction. The read buffer in the SDRAM controller should be
enabled for optimal performance, especially during memory-read-multiple commands by
external PCI bus masters.