AMD Elan SC520, Руководство пользователя, Страница: 378 / 444

System Test and Debugging
24-4 Élan™SC520 Microcontroller User’s Manual
■
When High, this signal indicates that either a GP-DMA initiator or an external PCI bus
master contributed to the current SDRAM write cycle (the CPU may also have
contributed).
■ A Low indicates that the CPU is the only master that contributed to this write cycle.
24.4.1.1.2 DATASTRB
The DATASTRB signal is useful for the external in-circuit emulation system to latch data
from the SDRAM interface, regardless of the programmed SDRAM timing.
■
When Low, data on the SDRAM data bus is invalid.
■ When High, data on the SDRAM data bus can be latched on the next rising edge of the
CLKMEMIN signal.
24.4.1.1.3 CF_ROM_GPCS
The CF_ROM_GPCS signal can be sampled on the Low-to-High transition of the ROMRD
signal during ROM/Flash cycles or during the Low-to-High transition of GPMEMRD for
GPCS7
± GPCS0 cycles.
■
The CF_ROM_GPCD signal should be sampled only when either GPMEMRD or
ROMRD is asserted.
■
When Low under these conditions, this signal indicates that the CPU is performing a
code fetch from ROM (on either the GP bus or SDRAM interface) or a GP bus memory
device.
24.4.1.2 Using the System Test Mode Interface
The system test mode interface is useful for tracing Am5
x
86 CPU activity on the SDRAM
and GP bus interfaces, including when the Am5
x
86 CPU is the initiator, when the data is
valid during SDRAM read and write cycles, and differentiating between code fetches and
data accesses. This still requires demultiplexing the BA1–BA0 and MA12–MA0 SDRAM
address bus to construct a full 28-bit address, which also requires knowledge of the
programming of some of the SDRAM controller configuration registers for device size and
symmetry. Since a data strobe is provided on the WBMSTR1 pin in this mode, detailed
knowledge of the programming of the SDRAM timing is not required. See Chapter 10,
“SDRAM Controller”, for details of SDRAM cycle timing and address multiplexing.
The CF_DRAM and CF_ROM_GPCS signals enable external determination of code
fetches from SDRAM, ROM/Flash, or any GP bus memory device. Prefetches from the
SDRAM controller’s read buffer can also be identified.
24.4.1.3 SDRAM Write Cycle in System Test Mode
Figure 24-1 illustrates the timing of a page hit SDRAM write cycle during system test mode.
To capture the CF_DRAM, BA1–BA0, MA12–MA0, and MD31–MD0 signals, the logic
analyzer or external in-circuit emulation system can use the DATASTRB signal to identify
the appropriate time to latch the information. This information must be captured on the
rising edge of CLKMEMIN when DATASTRB is sampled active. Note that DATASTRB is
not asserted during the read portion of a read-modify-write cycle that occurs for sub-
doubleword writes with ECC enabled.