AMD Elan SC520, Руководство пользователя, Страница: 161 / 444

PCI Bus Host Bridge
Élan™SC520 Microcontroller User’s Manual 9-13
Figure 9-8 CPU Read Cycle to the PCI Bus
The following sequence annotates the Am5
x
86 CPU read cycle to the PCI bus shown in
Figure 9-8.
■ Clock #1: The Am5
x
86 CPU starts a read cycle to the PCI bus.
■
Clock #2: Note that blast is asserted by the Am5
x
86 CPU signaling a non-burst transfer.
If this were a burst read cycle, the Am5
x
86 CPU would deassert blast, but because the
PCI host bridge returns rdy to the Am5
x
86 CPU instead of brdy, the Am5
x
86 CPU would
break up the burst into single cycles. A posted write cycle pending in the master posted
write buffer would delay the completion of the Am5
x
86 CPU read cycle.
■ Clock #6: The PCI host bridge master controller has synchronized the Am5
x
86 CPU
bus request and asserts req to gain access to the PCI bus. Because the Am5
x
86 CPU
is the initiator of the cycle, the bus request signal is not seen externally.
■
Clock #7: The PCI host bridge gnt signal is sampled asserted, and the PCI bus is idle,
so FRAME is asserted to begin the PCI bus transaction. In this example, there is no
arbitration delay (the arbiter is parked on the host bridge). If another external PCI bus
master was granted the bus, or the bus was not idle, FRAME assertion would be delayed
until the host bridge’s gnt was asserted and the bus was idle.
■ Clock #9: The external PCI bus target asserts TRDY, indicating that the requested data
is available. In this example, the PCI bus target did not add any wait states to the
transaction. A PCI bus Revision 2.2-compliant target can add up to 16 wait states that
would delay the PCI bus transaction and subsequent Am5
x
86 CPU cycle completion.
An external PCI bus target can also issue a retry that would delay the PCI bus transaction
and subsequent Am5
x
86 CPU cycle completion (see Section 9.5.3.4.2).
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GDWDLQ
DGGUHVV
GDWDLQ
UHDGFPG E\WHHQDEOHV
clk
ads
cycle_info
rdy
blast
CPU Data
pcihit
ADx
CBEx
FRAME
IRDY
TRDY
DEVSEL
req
gnt
Notes:
The diagram includes the following internal signals:
• pcihit: Address decode signal that the current Am5
x
86 CPU cycle is a PCI cycle.
The clk signal denotes the 33-MHz clock source and represents both the CPU clock and the PCI clock. This diagram
does not represent the full synchronization of signals between these clock domains.