AMD Elan SC520, Руководство пользователя, Страница: 211 / 444

SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-33
Precharge command closes all open pages in the SDRAM devices, thus placing them in
an idle state. This also forces the SDRAM controller’s page table entries to be invalidated.
The column address requirement of the device specifies its symmetry (i.e., its usable
number of columns, or page width, that the SDRAM controller can utilize), but does not
specify the amount of addressable SDRAM in the 32-bit bank. The bank ending address
is used to specify the physical address boundary of each bank. The bank ending address
is independent of device density or device data width. During SDRAM sizing, a bank should
never be enabled with a bank ending address of 0. The internal bank count specifier is
used to inform the SDRAM controller of the internal bank architecture of the device, since
SDRAM devices can contain either two or four internal banks.
■
To dynamically determine the amount of SDRAM memory in the entire system, the sizing
algorithm must first determine the amount of SDRAM installed per each external bank.
– To do this, the algorithm must enable one external bank at a time and start with the
largest possible configuration for that bank, which is 11 columns, 4 internal banks,
and 13 rows.
– If a smaller-sized SDRAM is installed in a given external bank, aliases will be created,
and the sizing algorithm uses the aliasing to determine the actual size of the external
SDRAM bank.
■
Note that while SDRAM sizing is being performed, the Am5
x
86 CPU cache, the SDRAM
ECC, the SDRAM write buffer, and the SDRAM read-ahead feature should all be
disabled.
For example, to setup external SDRAM Bank 3 to its largest possible SDRAM configuration
setting, a value of A000h should be written into the SDRAM Bank Configuration (DRCCFG)
register (MMCR offset 14h), and a value of FF000000h should be written into the SDRAM
Bank 0–3 Ending Address (DRCBENDADR) register (MMCR offset 18h).
10.6.4.1 Determining the Number of Columns for an External Bank
Determining the correct number of columns for a given external bank of SDRAM can be
accomplished by four writes and five reads of a given external bank.
Four unique data patterns must be selected.
An example is:
pattern1 = 0Bh
pattern2 = 0Ah
pattern3 = 09h
pattern4 = 08h
Four SDRAM memory addresses must be selected that all have the same internal bank
and SDRAM row address bits (processor address bits 31–13 constant) and the same low
order column address bits (processor address bits 9–0 constant), but with specially selected
column addresses for processor address bits 12–10.
■ The first address must have SDRAM column address bits 11, 9, and 8 (processor address
bits 12–10) on.
■
The second address must have SDRAM column address bit 11 (processor address bit
12) off and SDRAM column address bits 9–8 (processor address bits 11–10) on.
■ The third address must have SDRAM column address bits 11 and 9 (processor address
bits 12-11) off and SDRAM column address bit 8 (processor address bit 10) on.