AMD Elan SC520, Руководство пользователя, Страница: 254 / 444

General-Purpose Bus Controller
13-10 Élan™SC520 Microcontroller User’s Manual
register (MMCR offset C01h) and the state of the GPIOCS16 and GPMEMCS16 signals.
The Am5
x
86 CPU then generates multiple 8-bit or 16-bit bus cycles until all 32-bit data is
accessed; thus, the size is transparent to software. This is true for read accesses and write
accesses.
If the GP Chip Select Data Width (GPCSDW) register is programmed for 8-bit data width,
assertion of external GPIOCS16 (during an I/O access) or GPMEMCS16 (during a memory
access) overrides the data width specified in the GP Chip Select Data Width (GPCSDW)
register, as discussed on page 13-19.
Unaligned address accesses (addresses that are not on the 16-bit address boundary) are
supported through the Am5
x
86 CPU. The Am5
x
86 CPU breaks an unaligned address bus
cycle into multiple bus cycles with appropriate byte enable signals (be3–be0). The GP bus
controller simply takes one Am5
x
86 CPU bus cycle at a time and generates one external
bus cycle at a time.
13.5.5 Sharing the Address and Data Bus with the ROM/Flash Controller
A ROM device’s data bus can be connected to either the GP bus data bus or the SDRAM
data bus.
■
When a ROM device is connected to the GP data bus, the ROM access shares both
GPD15–GPD0 and GPA25–GPA0 with the GP bus.
■
When a ROM device is connected to the SDRAM data bus, the ROM access shares
only GPA25–GPA0 with the GP bus.
This does not cause bus contention, because only the Am5
x
86 CPU can initiate an access
to either ROM or to the GP bus. Since the Am5
x
86 CPU can perform an access to only
one controller at a time, no conflict is possible.
Note that the GP bus DMA controller can initiate an access on the GP bus. Since the GP
bus DMA controller must already own the Am5
x
86 CPU’s bus before it can initiate an access,
once again, there can be no conflict between bus cycles initiated by the GP bus DMA
controller and ROM cycles initiated by the Am5
x
86 CPU.
Note that the ROM devices are cacheable, but GP bus devices are noncacheable. This is
because the ROM controller supports cacheability and has its own independent control
signals (chip selects, read strobe, and write strobe).
13.5.6 GP Bus Echo Mode
In normal operation, the integrated peripheral accesses are not visible on the external pins.
GP bus echo mode is provided to view accesses to the internal GP bus peripherals on the
external pins. This feature aids in debugging system software and boot code. This applies
to the integrated peripherals only (timers, GP-DMA controller, UARTs, SSI, RTC, etc.) and
not to the memory or PCI bus controllers.
Accesses to internal peripherals that are “echoed” out utilize the programmable timing set
to ensure that there is no timing conflict with other external peripherals. Typically, internal
peripheral bus accesses are faster than external peripherals. Therefore, when using GP
bus echo mode to debug the system, be aware that accesses to the integrated peripherals
may be occurring at slower speeds to ensure compatibility with external devices, thus
resulting in a slower system performance.
When GP bus echo mode is enabled, GPAEN is driven high during accesses from the
Am5
x
86 CPU to internal peripherals to prevent external devices from decoding (or
responding to) these internal peripheral accesses. In normal operation (GP bus echo mode
disabled), the GP bus controller never asserts GPAEN.