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System Arbitration
8-6 Élan™SC520 Microcontroller User’s Manual
Figure 8-3 CPU Bus Rotating Priority Queue
8.4.2.2 CPU Cache Snooping
The Am5
x
86 CPU includes a write-back cache that updates only the internal cache on
memory writes from the CPU (if configured for write-back mode). When only the internal
cache memory is updated for a memory write, the external SDRAM contains invalid data.
Thus, snooping is required to maintain coherency when other bus masters are accessing
SDRAM. Any time another master (GP-DMA or PCI host bridge) is accessing a SDRAM
location that contains stale data (valid data is in Am5
x
86 CPU cache), the valid cache data
must be written back to SDRAM before the other master is allowed access to the SDRAM.
Therefore, all non-Am5
x
86 CPU accesses to SDRAM (both reads and writes) are snooped
by the Am5
x
86 CPU.
The Am5
x
86 CPU cache can be optionally configured to operate in write-through cache
mode by setting the CACHE_WR_MODE bit in the Am5
x
86 CPU Control (CPUCTL) register
(MMCR offset 02h). In this mode, both the internal cache and external memory are updated
on memory writes. Because the external memory is updated, there are no cache data
concurrency issues due to Am5
x
86 CPU memory writes. Other master write cycles are still
snooped, however, to keep the Am5
x
86 CPU’s cache coherent with external memory. In
this case, the external memory is updated, and the cache contains invalid data. The snoop
invalidates this internal cache location to maintain coherency. There is no overhead involved
with snooping when the cache is configured for write-through cache mode. The snoop
happens during the cycle (no preemption, write-back, or additional wait-states are inserted).
The ÉlanSC520 microcontroller does not support dynamic cache-write policy changes.
8.4.2.3 Accessing the PCI Host Bridge Target
The PCI host bridge allows external PCI bus masters to read and write the ÉlanSC520
microcontroller’s SDRAM. Two 64 doubleword FIFOs (one read, one write) in the
ÉlanSC520 microcontroller’s host bridge are used to increase PCI bus performance. Once
granted the bus by the CPU bus arbiter, the PCI host bridge target controller is allowed to
prefetch up to 64 DWORDs (for a memory-read-multiple command), or write (memory-write
or memory-write-and-invalidate commands) up to 64 doublewords before the bus is granted
to another master. During this time, no other master is granted the CPU bus. The Am5
x
86
CPU, however, is granted the bus during this time to write back a cache location if necessary.
CPU
GP Bus
DMA
Host
Bridge
Target