AMD Elan SC520, Руководство пользователя

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Élan™SC520 Microcontroller User’s Manual 11-1
CHAPTER
11
WRITE BUFFER AND READ BUFFER
11.1 OVERVIEW
The ÉlanSC520 microcontroller includes two buffering techniques to optimize the SDRAM
system performance. These include a write buffer and a read buffer with a read-ahead
feature.
The write buffer provides a mechanism for all masters (Am5
x
86 CPU, PCI, or GP-DMA) to
post write data with zero wait states. When enabled, the write buffer effectively decouples
master write activity from incurring the SDRAM latency penalty. This, in effect, also allows
SDRAM to satisfy a higher demand in read activity by all masters. In addition, the write
buffer provides write-merging and write-collapsing functions to better utilize FIFO storage
and reduce the total number of transactions to SDRAM. Data read-merging is also
supported to efficiently maintain data coherency.
The read buffer provides two cache lines (32 bytes total) of storage for read data returned
from SDRAM. The read buffer and its associated read-ahead function, when enabled,
provide a mechanism to prefetch the cache line of information from SDRAM that
immediately follows the requested cache line. This feature is provided in anticipation of
future accesses to the prefetched line (spatial locality). The read buffer is always enabled;
however, the read-ahead feature and write buffer are disabled after a system reset.
Although both the write buffer and read-ahead feature of the read buffer are tightly
integrated, they can be independently enabled.
Features of the write buffer include:
■ 32-level doubleword FIFO with random access capability
■
Content addressable memory (CAM) provides snoop capability
■ Zero wait state writes to non-full buffer
■
Provides write-merging, write-collapsing, and read-merging functions
■ Benefits Am5
x
86 CPU, PCI, and GP-DMA SDRAM write transfers
Features of the read buffer include:
■
Read buffer provides storage for two Am5
x
86 CPU cache lines (32 bytes total)
■ Zero wait state reads on read buffer hits
■
Read-ahead feature that, when enabled, prefetches the next cache line of information
from SDRAM for master read requests of two or more doublewords
■
Demand doubleword start fetch
■ Benefits Am5
x
86 CPU, PCI, and GP-DMA SDRAM read transfers
The write buffer is expected to enhance individual write or burst write activity by all masters.
It supplies zero wait state writes for all masters. However, the write buffer’s write-merging
and write-collapsing features greatly enhance Am5
x
86 CPU, PCI, and GP-DMA 8-bit and